Part II - Analog and mixed-mode IC design

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The second part of the WorkBook…

technology-independent tutorials vanilla environment setups simple SPICE model files that can be downloaded without restrictions from the Web

Although layout exercises have been run attached to a specific technology, no technology references will be included in the tutorials description. As a matter of fact we mention a few very standard layers (e.g. M1 and M2 metal layers) which are common to all technologies.

Layout examples with the LayoutEditor open source software

extract a simple sandwitch metal-to-metal capacitor, which is another technology-independent example

To get started with SPICE you can refere to LTspice pages

A collection of questions abaout analog design with Cadence has been collected in form of HowTo's and FAQs.

• Getting started
  • Introduction
  • Tools overview
  • Reference documentation
  • Setting up the UNIX evironment
  • Running Cadence Virtuoso
  • Quitting the session

• Analog design infrastructure
  • Introduction
  • Technology files, libraries, LEF/DEF etc.

• Design hierarchy
  • Introduction
  • Libraries
  • The cds.lib file
  • Cells
  • Cell views
  • Using the Library Manager
  • Creating a new library
  • Creating a new cell
  • Opening an existing cell
  • Copying and deleting
  • Managing libraries with the Library Path Editor

• Cadence environment and setup files
  • Introduction
  • Reference documentation
  • Sample files
  • .cadence directories
  • .cdsenv and .cdsinit initialization files
  • .cdsinit_tech
  • libInit.il
  • CDS.log
  • .simrc
  • .cdsplotinit
  • cds.lib library definition file
  • display.drf
  • Bindkeys
  • Some customization examples

• Basic analog design tutorials
  • Introduction
  • Environment setup
  • Tutorial 1 - Basic NMOS characteristics
  • Tutorial 2 - Common-source amplifier
  • Tutorial 3 - The CMOS inverter
  • Tutorial 4 - A two stage OPAMP with Miller compensation
  • Tutorial 5 - …
  • Tutorial 6 - …
  • Third party video tutorials

• Schematic-entry references
  • Introduction
  • ….
  • Iterated instances (vectors)
  • …
  • …

• Simulation references
  • Introduction
  • Reference documentation
  • DC operating points
  • Power consumption evaluation
  • ADE simulation options
  • Total input/output impedance simulation
  • Noise analyses
  • ….

• Design techniques
  • Introduction
  • MOS small signal model validity
  • Analog design in very deep submicron technologies
  • Rules of thumb for transistor sizing
  • Some standard analog topologies

• Bad analog design practices
  • Introduction
  • …

• Advanced analog design simulations
  • Introduction
  • Getting started with ADE XL
  • Reference documentation
  • Corner analysis
  • Monte Carlo simulations

• Include documentation in your designs
  • Introduction
  • Add notes and comments to schematics
  • Creating text cell views
  • Include documentation in ADE XL
  • Datasheets generation
  • …

• Running simulations using OCEAN
  • Introduction
  • Reference documentation
  • …
  • …

• Introduction to Mixed-Signal simulation with Cadence tools
  • Introduction
  • …
  • …

• Layout (an introduction)
  • Introduction
  • Tools overview
  • Reference documentation
  • Environment setup
  • Load standard bindkeys
  • Starting Cadence Virtuoso Layout Editor L/XL
  • Setting user preferences
  • The Layer Palette

• Basic layout tutorials
  • Introduction
  • Create a ruler
  • Draw a simple metal layer
  • Edit objects
  • Merge layers
  • View the layer stack
  • Create a text label
  • Create a pin

• Working with parametrized cells
  • Introduction
  • Substrate contacts
  • NMOS layout
  • PMOS layout

• Basic layout techniques
  • Introduction
  • Multi-finger transistors
  • Common centroid layout
  • Latch-up

• Standard layout examples
  • Inverter layout
  • Common source amplifier
  • NAND gate
  • NOR gate
  • Differential pair
  • Ring oscillator

• Post-Layout simulations
  • Introduction
  • Parasitic extraction
  • Simulation of the extracted netlist

• Full example: a parallel-plates capacitor

• HowTo's

• FAQs

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Maintainers: Alessandra Lattuca, Luca Pacher
Last update: Luca Pacher - Arp 10, 2013