Analog IC design HowTo's

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How to change the default simulation results and saved states directories

By default, all simulation data and results are stored in a ~/simulation directory automatically created in your home directory the first time you run a simulation with Cadence IC. Similarly, Cadence simulation states by default are saved in a ~/.artist_states hidden directoryautomatically created in your home directory.

To change these defaults, just use in your home ~/.cdsinit or ~/.cdsinit_personal files the following directives:

envSetVal("asimenv.startup" "projectDir" 'string "/path/to/your/custom/simulation/results/directory")
envSetVal("asimenv" "saveDir" 'string "/path/to/your/custom/simulation/states/directory")


You can also issue these statements at the CIW command prompt.


See also

http://www.cadence.com/Community/forums/p/17009/1179512.aspx

Solo pe rla sessione corrente:

CIW ⇒ Options ⇒ User Preferences…

poi nel Command Controls tab c'e' la Beep Volume section

Altrimenti si customizza l'environment editanto il .cdsinit

A detailed Wiki page about this topic has been created, please refer to Power consumption evaluation in Cadence.

To set the default simulator, e.g. as Spectre, enter the following environment variable in your .cdsenv or .cdsinit file. Syntax to set the default simulator in the .cdsenv

asimenv.startup simulator string "spectre"

Syntax to set the default simualtor in the .cdsinit

envSetVal("asimenv.startup" "simulator" 'string "spectre")

Syntax to set the default model path in the .cdsenv

spectre.envOpts modelPath string "<pathTo>/myModelFile;section"

Syntax to set the default model path in the .cdsinit

envSetVal("spectre.envOpts" "modelPath" 'string "<pathTo>/myModelFile;section")

e.g. creare un ideal OPAMP with a vcvs

pPar("gain")

CIW ⇒ Tools ⇒ CDF ⇒ Edit…

see also here

save M0:oppoints

Other web tutorials can be found here and here

riseTime(.....)
delay(......)

Example: Time-over-Threshold

This is a very useful trick to make your schematics more readable. Diagonal connections are used to draw cross-coupled transistors as in latches and flip-flops.

Press W to begin wiring, then press the F3 key. The Add Wire window will appear.

Change the Draw Mode from the default of “route” to something that allows diagonal or any angle wires.

You can also specify a 45 degree fixed angle with the relative Lock Angle option.

But you can also change between different Draw Modes simply by clicking on the mouse whell or the central mouse button!

See also

http://www.cadence.com/Community/forums/p/16772/1178636.aspx

Se e' installato

see also here

A detailed Wiki page about this topic has been created, please refer to Node impedance simulation.

In ingresso tipicamente e' quella vista sul gate of the input transistor

OP("/M0","cgg")

Si applica la definizione, mando in ingresso un voltage step e misuro

SR = max{d vout / dt }

ymax(deriv(VT("/out")))

in potenze di 2, as Manuel dixit?

cd ~/cadence
mkdir ideal_blocks
cd ideal_blocks
mkdir idealLib

poi create a cds.lib with the following directives:

INCLUDE $IC_DIR/tools/dfII/local/cds.lib
DEFINE idealLib $HOME/cadence/ideal_blocks/idealLib

poi lanciare virtuoso normalmente



Last update: Luca Pacher - Apr 23, 2013

  • vlsi/workbook/analog/howtos.txt
  • Ultima modifica: 29/11/2013 11:24
  • da pacher