VLSI Design WorkBook [ADVANCED TOPICS]

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At present, just a random list of pages about advanced topics…

• SKILL programming
• OpenAccess references
• Converting existing libraries from CDB to OA
• Understanding technology files
• Creating config views for testbenches and post-layout simulations
• Writing a liberty file for the analog Front-End
• Scripting with Calibre DRC/LVS/RCX
• Gate-level simulations (with SDF back annotation)
• Using Makefiles (Cadence Incisive, RTL Compiler, EDI)
• PADs insertion with Encounter
• VHDL simulation using GHDL compiler/simulator
• GTKWave
• List of most important Cadence environment variables
• Synopsys Design Constaints (SDC)
• Standard Delay Format (SDF) annotation and simulation
• Sign-Off
• Multiple clock synthesis
• Importing and exporting GDS
• Importing and exporting LEF/DEF
• Understanding map files
• Tapeout procedures
• Automated Digital Block Implementation using Virtuoso
• Automated mixed-signal routing using Virtuoso Space-Based Router (VSR)
• Library characterization using Virtuoso Liberate

Last update: Luca Pacher - Sep 16, 2014