Modifica questa pagina Puntano qui Rename Page Fold/unfold all Puntano qui Questa è una lista delle pagine che sembrano avere un collegamento alla pagina attuale. VLSI Design WorkBookScripting with Calibre DRC/LVS/RCXConverting existing libraries from CDB to OAList of most important Cadence environment variablesMultiple clock synthesis with RTL CompilerCreating config views for testbenches and post-layout simulationsGate-level simulations (with SDF annotation)Importing and exporting GDS (Cadence IC 6.1.x / EDI)GHDL VHDL compiler and simulatorGTKWave waveform viewerImporting and exporting LEF librartiesLibrary characterization using Virtuoso Liberate toolsWriting a liberty file for the analog Front-EndUsing makefiles to automate digital design tasksUnderstanding layer/via map files for GDSII import/exportOpenAccess (OA)Inserting PADs with EncounterSynopsys Design Constraints (SDC)Standard Delay Format (SDF) annotation and simulationDesign finishing and signoff analysesSKILL programming referencesTapeout proceduresUnderstanding technology filesAutomated Digital Block Implementation Using Virtuoso Layout (G)XLAutomated mixed-signal routing with Virtuoso Space Router (VSR)