Synopsys Design Constraints (SDC)

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Reference documentation from Synopsys:

Synopsys Timing Constraints and Optimization User Guide (tcoug.pdf)
http://acms.ucsd.edu/_files/tcoug.pdf

http://www.synopsys.com/Community/Interoperability/Pages/TapinSDC.aspx

Documentation from Cadence:

Setting Constraints and Performing Timing Analysis Using Encounter RTL Compiler (rc_ta.pdf)
<install dir>/doc/rc_ta/rc_ta.pdf

Useful external links:

http://www.vlsi-expert.com/2011/02/synopsys-design-constraints-sdc-basics.html

http://www.microsemi.com/document-portal/doc_download/131597-design-constraints-guide

http://application-notes.digchip.com/056/56-39741.pdf

We can list all of the supported SDC commands with:

rc:/> foreach cmd [lsort [info commands dc::*]] {puts $cmd}

::dc::add_to_collection
::dc::all_clocks
::dc::all_fanin
::dc::all_fanout
::dc::all_inputs
::dc::all_instances
::dc::all_outputs
::dc::all_registers
::dc::append_to_collection
::dc::check_override
::dc::compare_collection
::dc::copy_collection
::dc::create_clock
::dc::create_generated_clock
::dc::current_design
::dc::current_instance
::dc::filter_collection
::dc::foreach_in_collection
::dc::get_cell
::dc::get_cells
::dc::get_clock
::dc::get_clocks
::dc::get_design
::dc::get_designs
::dc::get_generated_clocks
::dc::get_lib
::dc::get_lib_cell
::dc::get_lib_cells
::dc::get_lib_pin
::dc::get_lib_pins
::dc::get_lib_timing_arcs
::dc::get_libs
::dc::get_net
::dc::get_nets
::dc::get_object_name
::dc::get_path_groups
::dc::get_pin
::dc::get_pins
::dc::get_port
::dc::get_ports
::dc::getenv
::dc::group_path
::dc::index_collection
::dc::remove_case_analysis
::dc::remove_clock_gating_check
::dc::remove_clock_latency
::dc::remove_disable_clock_gating_check
::dc::remove_from_collection
::dc::remove_generated_clock
::dc::remove_ideal_net
::dc::remove_ideal_network
::dc::remove_input_delay
::dc::remove_output_delay
::dc::set_annotated_transition
::dc::set_case_analysis
::dc::set_clock_gating_check
::dc::set_clock_groups
::dc::set_clock_latency
::dc::set_clock_sense
::dc::set_clock_skew
::dc::set_clock_transition
::dc::set_clock_uncertainty
::dc::set_data_check
::dc::set_disable_clock_gating_check
::dc::set_disable_timing
::dc::set_dont_touch
::dc::set_dont_touch_network
::dc::set_dont_use
::dc::set_drive
::dc::set_driving_cell
::dc::set_equal
::dc::set_false_path
::dc::set_fanout_load
::dc::set_hierarchy_separator
::dc::set_ideal_net
::dc::set_ideal_network
::dc::set_input_delay
::dc::set_input_transition
::dc::set_lib_pin
::dc::set_lib_pins
::dc::set_load
::dc::set_load_unit
::dc::set_logic_dc
::dc::set_logic_one
::dc::set_logic_zero
::dc::set_max_capacitance
::dc::set_max_delay
::dc::set_max_dynamic_power
::dc::set_max_fanout
::dc::set_max_leakage_power
::dc::set_max_time_borrow
::dc::set_max_transition
::dc::set_min_delay
::dc::set_multicycle_path
::dc::set_operating_conditions
::dc::set_opposite
::dc::set_output_delay
::dc::set_path_adjust
::dc::set_port_fanout_number
::dc::set_time_unit
::dc::set_timing_derate
::dc::set_unconnected
::dc::set_units
::dc::set_wire_load_mode
::dc::set_wire_load_model
::dc::set_wire_load_selection_group
::dc::sizeof_collection
::dc::sort_collection

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