---

First of all, we have to decide what kind of project we're going to do in VHDL language.

In the following tutorial we'll develop a very simple shift register in order to understand the first steps of ASIC programming. It is necessary to create a well organized working space in order to avoid confusion among files and directories that we'll use during the digital flow.

To be ordered is extremely important in life! and also here could let you avoid wasting a lot of time…

In the following picture you can see an example of directories' tree for our project:

In the projects directory another directory shiftregister has been created, and this one will contain all the files pertinent with the project (with the exception of the technology libraries)

Even if we won't use immediately all the directories, we can create them right now; in the shiftregister directory we can see:

• lec (logic equivalence check)
  
• pnr_shiftregister (ci servirà per il place and route)
  
• syn_shiftregister (ci serve per la sintesi, ed è la cartella che prenderemo in considerazione ora).
  

Into syn_shiftregister directory we can prepare others directories:

• db
  
• netlist_in
  
• netlist_out
  
• reports
  
• scripts
  
• sdc
  
• work
  

Now, in the netlist_in directory, we can create two empty files with a .vhd extension:

• the first, we will name shiftregister.vhd (this is the source file),
• the second, tb_shiftregister.vhd (this is the test bench file).

Note that, in order to have a simpler life in the later steps (simulation and synthesis) and in order to recognize immediately which file is a source file and which is a test bench file, we could name the source file with the same name of the entity, (i.e. shiftregister.vhd) and the test bench file with the same name of the source file with the exception of a tb_ suffix (i.e. tb_shiftregister.vhd).

In the case we have some test benches, we can also enumerate them, in this way: tb01_shiftregister.vhd, tb02_shiftregister.vhd, tb350_shiftregister.vhd etc. Here we'll use only one test bench, so we won't enumerate the file.

In our example, we decided to implement a shift register in which we have serial input and output (they're standard logic); so we have just defined an object like this:

Now we can decide if we want a positive or a negative logic; in the first case we consider the TRUE case equal to 1 and the FALSE case equal to 0; in the second one, it is just the opposite.

We can write, then, the VHDL model including the process that allow us to select the right output:

-- *********************************************
-- Title	: 3-bit Shift-Register
-- Author	: Serena Panati
-- File		: shiftregister.vhd
-- Version	: 1.0
-- Generated	: 09.03.2013
-- *********************************************
----------------------------------------
-- Libraries
----------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
----------------------------------------
-- Entity declaration
----------------------------------------
entity shiftregister is
port(	data_in:	in std_logic;
	sr_clock:	in std_logic;
	shift:		in std_logic;
	Q:		out std_logic
);
end shiftregister;
----------------------------------------
-- Architecture
----------------------------------------
architecture shiftregister_archi of shiftregister is
-- inizializzazione del segnale S
    signal S: std_logic_vector(2 downto 0):="111";
begin 
    process(data_in, sr_clock, shift, S)
    begin
	if sr_clock'event and sr_clock='1' then
	    if shift = '1' then
		S(0) <= data_in;
		S(2 downto 1) <= S(1 downto 0);
	    end if;
	end if;
    end process;
    Q <= S(2);
end shiftregister_archi;
----------------------------------------
-- EoF
----------------------------------------

and then we save it.

Now it is necessary to write a test bench file, like this:

-- *********************************************
-- Title	: TB 3-bit Shift-Register
-- Author	: Serena Panati
-- File		: tb_shiftregister.vhd
-- Version	: 1.0
-- Generated	: 09.03.2013
-- *********************************************
----------------------------------------
-- Libraries
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;  
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
----------------------------------------
-- Entity declaration
----------------------------------------
entity tb_shiftregister is	
	generic ( clock_period : time := 10 ns);  	
end tb_shiftregister;
----------------------------------------
-- Architecture
----------------------------------------
architecture tb_shiftregister_archi of tb_shiftregister is
    component shiftregister
    port(   data_in:	in std_logic;
	    sr_clock:	in std_logic;
	    shift:	in std_logic;
	    Q:		out std_logic
    );
    end component;
 
    signal T_data_in:	std_logic;
    signal T_sr_clock:	std_logic;
    signal T_shift:	std_logic;
    signal T_Q:		std_logic;
begin
    instance_shiftregister: shiftregister 
port map ( 
	data_in  => T_data_in,
 	sr_clock  => T_sr_clock, 
	shift  => T_shift, 
	Q  => T_Q);
----------------------------------------
-- clk generating process
----------------------------------------
generate_clock : process 
	begin
	T_sr_clock   <= '1';
		wait for clock_period/2;
	T_sr_clock   <= '0';
		wait for clock_period/2;
	end process;
----------------------------------------
-- Values generating process
----------------------------------------
 process
    begin
	wait for clock_period;								
	T_shift <= '1';			
	T_data_in <= '0';
	wait for clock_period;
	T_data_in<= '1';	 		
	wait for clock_period;
	T_data_in <= '0';		
	wait for clock_period;
	T_data_in <= '1';	
	wait for clock_period;		
 assert FALSE report "End of simulation" severity FAILURE;
    end process;
----------------------------------------
end tb_shiftregister_archi;
----------------------------------------
-- Configuration File
----------------------------------------
configuration tbc_shiftregister_archi  of tb_shiftregister  is 
        for tb_shiftregister_archi
                for all: shiftregister			
                        use entity work.shiftregister(shiftregister_archi);
                end for;
        end for;
end tbc_shiftregister_archi ;
----------------------------------------
-- EoF
----------------------------------------

In the test bench code we can see the instantiation of the component that we want to simulate (in this example, we have only one component, but VHDL allows instantiation of more than one component); in addition, there are the definitions of internal signals, port-signal mapping and various processes in order to force inputs to 0 or 1 values.

In this example, we can see that the shift-process is active and input values are forced after a clock period.

Line

assert FALSE report "End of simulation" severity FAILURE;

represents a trick in order to stop the simulation when the last values is forced, without stopping it using the GUI of Cadence SimVision.

The last part of this code represents the configuration file that connects each component to its entity.

----------------------------------------
-- Configuration File
----------------------------------------
configuration tbc_shiftregister_archi  of tb_shiftregister  is 
        for tb_shiftregister_archi
                for all: shiftregister			
                        use entity work.shiftregister(shiftregister_archi);
                end for;
        end for;
end tbc_shiftregister_archi ;

For the simulation we can use Cadence NCLaunch e SimVision tools.

Let's move from home directory to netlist_in:

cd projects/shiftregister/syn_shiftregister/netlist_in/

and let's write

cdsterm

and let's press Enter; then we can choose the tool with:

1d

and press Enter another time; then let's select the technology we want to use; in this example, we'll choose Tower Jazz, so:

5a

and then Enter. A new terminal will open, and in this window writing

nclaunch &

and pressing Enter, the window showed in the following picture will appear.

Now, it is possible to compile the file by clicking two times on shiftregister.vhd (left column) or by selecting the name and then clicking on the VHDL button (with a gear symbol).

Below into the console, it is possible to see the script of the command, error signals (if there were), memory and CPU use; in our case:

nclaunch> ncvhdl -work worklib -cdslib /export/elt78xl/disk0/users/panati/
projects/shiftregister/syn_shiftregister/netlist_in/cds.lib -logfile
ncvhdl.log -errormax 15 -update -linedebug -status /export/elt78xl/
disk0/users/panati/projects/shiftregister/syn_shiftregister/
netlist_in/shiftregister.vhd
ncvhdl(64): 10.20-s073: (c) Copyright 1995-2011
Cadence Design Systems, Inc.
ncvhdl_p: Memory Usage - 10.4M program + 13.2M data = 23.6M total
ncvhdl_cg: Memory Usage - 7.6M program + 10.7M data = 18.3M total
ncvhdl: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.3s, 8.7% cpu)

The procedure for the test bench is totally the same.

In the case of error, i.e. forgetting in line 49 the last semicolon:

T_sr_clock <= ’1’

instead of

T_sr_clock <= ’1’ ;

we can read some warnings in the console, specifying the error type (expecting semicolon) and the line in which there it is (49).

In this way it is possibile debugging codes until they are without errors or problems.

Then we can elaborate our project. In the right column, under the worklib directory, there are three IC symbols, with some titles:

• shiftregister
  
• tb_shiftregister
  
• tbc_shiftregister
  

we have to select the tbc_shiftregister (configuration file) and then clicking on the Elaboration button (with a clip image, Launch Elaborator).

If there aren't problems, in console we will see only control messages (CPU and memory use) like this:

nclaunch> ncelab -work worklib -cdslib /export/elt78xl/disk0/users/
panati/projects/shiftregister/syn_shiftregister/netlist_in/cds.lib
-logfile ncelab.log -errormax 15 -access +wc -status
worklib.tbc_shiftregister_archi
ncelab(64): 10.20-s073: (c) Copyright 1995-2011 Cadence Design Systems, Inc.
ncelab: Memory Usage - 31.7M program + 30.9M data = 62.6M total
ncelab: CPU Usage - 0.0s system + 0.0s user = 0.1s total (0.7s, 10.0% cpu)

At the same time, in the Snapshot directory (second column under worklib) worklib: tbc_shiftregister_archi:configuration file will appear: we have to select it and then click on the Simulator button (Launch Simulator, to the right of Launch Elaborator).

In this moment two SimVision windows will open: DesignBrowser and Console:

Let's consider the DesignBrowser window: expanding the menu in the left column (WORKLIB:TB$\_$SHIFTREGISTER(TB_SHIFTREGISTER_ARCHI)) we can see the two processes of the test bench (generate_clk e values_gen) and the instance instance_shiftregister.

• By clicking on (WORKLIB:TB_SHIFTREGISTER(TB_SHIFTREGISTER_ARCHI)) in the right column signals will appear.

• By clicking on the instance (instance_shiftregister) input and output will appear.

Now it is possible to select signals or pin in order to simulate them; in this example both groups are simulated.

Starting by (WORKLIB:TB_SHIFTREGISTER(TB_SHIFTREGISTER_ARCHI)) we can select the signals in the right column (doing this they'll appear highlighted) and then we can click on the button with a red/green square waveform; then a new window named Waveform 1 will open.

Now we have to select some (or all) the line in the left column and by clicking Menu Simulations → Run (or simply F2) the waveforms will be drawn.

The first time the simulation is done, two files are created automatically in the netlist_in folder:

• cds.lib
• hdl.var

containing some information about the libraries for the simulation.

If we are using a choosen technology, in order not to have problems with the post-synthesis simulation, we can add in these files the paths of our technology libraries.

In this example, we are using Tower Jazz 180 nm technology (if you are using another technology, please ask your supervisor what path you need).

So, after the first simulation we have, i.e., in cds.lib:

define worklib /export/elt78xl/disk0/users/panati/projects/shiftregister/
syn_shiftregister/netlist_in/INCA_libs/worklib
include $CDS_INST_DIR/tools/inca/files/cds.lib

and in hdl.var:

define WORK worklib
include $CDS_INST_DIR/tools/inca/files/hdl.var

Then, we can change only the cds.lib in this way:

define worklib /export/elt78xl/disk0/users/panati/projects/shiftregister
/syn_shiftregister/netlist_in/INCA_libs/worklib
include $CDS_INST_DIR/tools/inca/files/cds.lib
DEFINE tsl18fs120_lib /usr/tj_lib/TS18IS_SC/tsl18fs120/verilog/tsl18fs120_lib

It is possible to export the waveforms in .pdf or .ps format (color or black and white), just open File → Print Window.

Here you can choose the document path, the title, the page size (A4, A5…), orientation, colors etc.

By using top-right buttons (+, -, =, magnifying glass…) it is possible to enlarge or shrink the waveform view.

The = symbol allows a synoptic vision.

You can change forced values in the test bench without closing Simvision. After the change, you can click on Simulation → Reinvoke simulator: in this way you can restart the Run (→ F2) with the newer values.

From column Cursor (the second beginning to the right) by right clicking it is possible to change the waveform color and the signal coding (binary, exaadecimal…).

Default for the standard logic: binary.

Default for the standard logic vectors: exadecimal.

By selecting some or all signals and by clicking on the button Schematic Tracer (the button with some little black wired boxes) it is possibile to have a useful tracer.

— Last Update: Serena Panati Nov 24st 2013