Part III - Digital IC design

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The third part of the WorkBook is dedicated to digital IC design…

Goal (in a wonderful world): build a standard cell library from scratch with simple SPICE models, extract liberty description of standard cells, create dummy layouts and abstract up to place-and-route !!! Everything… technology-independent !!!

Static timing analysis:
http://en.m.wikipedia.org/wiki/Static_timing_analysis

• Getting started
  • Introduction
  • Tools overview
  • Reference documentation
  • Setting up the UNIX environment

• Cadence environment and setup files
  • Introduction
  • ….
  • ….

• Basic digital CMOS
  • Introduction
  • ….
  • ….

• Verilog/VHDL simulation
  • Introduction
  • Build your own Cadence Incisive documentation repository
  • Verilog/VHDL references and documentation
  • Verilog simulation tutorials
  • VHDL simulation tutorials
  • …

• Build a standard cell library from scratch
  • Introduction
  • …
  • …

• Digital synthesis
  • Introduction
  • Getting started with Cadence RTL Compiler
  • Power Analysis
  • Verilog Digital synthesis tutorials
  • VHDL Digital synthesis tutorials
  • …

• Logic equivalence checking (LEC)
  • Introduction
  • Tools overview
  • Reference documentation
  • …

• Automatic place and route (PNR) with Cadence Encounter
  • Introduction
  • Tools overview
  • Reference documentation
  • Verilog Place and Route tutorials
  • VHDL Place and Route tutorials
  • Power Analysis
  • Importing gdsII in Virtuoso
  • …

• HowTo's

• FAQs

Last update: Luca Pacher - Sep 10, 2013