Verilog/VHDL simulation
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Contents
Introduction
Build your own Cadence Incisive documentation repository
Per Cadence Incisive invece la documentazione e' in
/usr/cadence/Incisive_10.20/doc/
cd ~/cadence/doc mkdir Incisive_10.20 cd Incisive_10.20 find /usr/cadence/Incisive_10.20/doc -name '*.pdf' -exec ln -s {} . \;
Verilog/VHDL references and documentation
I tutorial forniscono gia' il codice Verilog/VHDL, quindi uno puo' anche non saperlo!
Alcune referenze on-line sono:
http://www.utdallas.edu/~kinchit.desai/index_files/verilog/default.htm
Overview of HDL simulators
http://en.wikipedia.org/wiki/List_of_HDL_simulators
http://www.asic-world.com/verilog/tools.html
Used in the WorkBook: Cadence Incisive environment, Xilinx ISE and ModelSim
Testbench generation
Nice website:
Cadence Incisive tutorial
Tutorial provided with the Cadence Incisive installation:
<install dir>/doc/iustutorial/iustutorial.pdf
Copy all necessary files in your local working area:
mkdir iustutorial cd iustutorial cp -r <install dir>/doc/iustutorial/examples/files .