Modifica questa pagina Puntano qui Rename Page Fold/unfold all Indice Questo è un indice di tutte le pagine disponibili ordinate per categorie. calcolo cms database elettronica grid gruppo3 gruppo4 jlab12 magic5 moveit playground rappresentanti_ricercatori sicurezza_sul_lavoro sistemi_dinamici_e_turbolenza tps user vlsi it people personalpages private projects resources theses wiki workbook workbook2 liberate skill Useful SKILL routines (random) Scripting with Calibre DRC/LVS/RCX Converting existing libraries from CDB to OA List of most important Cadence environment variables Multiple clock synthesis with RTL Compiler Creating config views for testbenches and post-layout simulations Gate-level simulations (with SDF annotation) Importing and exporting GDS (Cadence IC 6.1.x / EDI) GHDL VHDL compiler and simulator GTKWave waveform viewer Importing and exporting LEF librarties Library characterization using Virtuoso Liberate tools Writing a liberty file for the analog Front-End Using makefiles to automate digital design tasks Understanding layer/via map files for GDSII import/export OpenAccess (OA) Inserting PADs with Encounter Synopsys Design Constraints (SDC) Standard Delay Format (SDF) annotation and simulation Design finishing and signoff analyses SKILL programming references Tapeout procedures Understanding technology files Automated Digital Block Implementation Using Virtuoso Layout (G)XL Automated mixed-signal routing with Virtuoso Space Router (VSR) INFN/CSN5 Short history VLSI Design Laboratory Wiki Home Page Info and coordinates Useful links and contacts VLSI lab Wiki Outreach personalpages VLSI Lab projects and design activities Publications People and contacts VLSI lab technology transfer activities VLSI Design WorkBook VLSI Design WorkBook [ADVANCED TOPICS] wiki header INFN Torino Wiki prova INFN Torino Wiki