Part V - Physical verification (DRC/LVS/PEX)

  • Introduction
  • Tools overview
  • Design rules
  • Design Rule Check (DRC)
  • Electrical Rule Check (ERC)
  • Layout-versus-Schematic (LVS)



Assura (Assura Physical Verification ) di per se' fa solo DRC e LVS!!!!!!!!!!!!!!!! La pex quella che si chiama Assura QRC in realta' e' fatta da un altro package, che si chiama Cadence QRC Extraction (che di fatto e' il sostituto di Assura RCX)!

Infatti sono 2 packages distinti, /usr/cadence/Assura_4.10oa-615 e /usr/cadence/EXT_9.13

the violation of any design rules would result in a higher probability (and in some cases an absolute certainty) that the fabricated chip does not work as desired!

When you do the layout it is always a good practice to perform DRC from time to time in order to identify mistakes earlier on! Otherwise if you decide to run DRC at the end of the layout you will get so many errors that you will not be able to identify and correctly fix them!





Last update: Luca Pacher - Apr 23, 2013

Last update:

  • vlsi/workbook/verification.txt
  • Ultima modifica: 14/10/2014 19:56
  • da pacher