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== Contents == | == Contents == | ||
- | * Introduction | + | * [[vlsi:workbook:digital:hdlsim#introduction|Introduction]] |
- | * ... | + | * [[vlsi:workbook:digital:hdlsim#build_your_own_cadence_incisive_documentation_repository|Build your own Cadence Incisive documentation repository]] |
- | * ... | + | * [[vlsi:workbook:digital:hdlsim#Verilog/VHDL_references_and_documentation|Verilog/VHDL references and documentation]] |
- | * Verilog and VHDL simulation examples | + | * [[vlsi:workbook:digital:hdlsim:verilog_tutorials|Verilog simulation tutorials]] |
+ | * [[vlsi:workbook:digital:hdlsim:vhdl_tutorials|VHDL simulation tutorials]] | ||
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+ | ===== Verilog/VHDL references and documentation ===== | ||
+ | |||
+ | I tutorial forniscono gia' il codice Verilog/VHDL, quindi uno puo' anche non saperlo! | ||
+ | |||
+ | Alcune referenze on-line sono: | ||
+ | * [[http://esd.cs.ucr.edu/labs/tutorial/|VHDL Tutorial: Learn by Example]] | ||
+ | * [[ http://asic.co.in/Index_files/tutorials/VHDL_Tutorial.htm | qua c'e' di tutto! ]] | ||
+ | * [[ http://en.wikipedia.org/wiki/VHDL | VHDL from Wikipedia]] | ||
+ | * [[ http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html | VHDL primer ]] | ||
+ | * [[ http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf | The VHDL Cookbook ]] | ||
+ | * [[ http://en.wikipedia.org/wiki/Verilog | Verilog from Wikipedia ]] | ||
+ | * [[ http://www.asic-world.com/verilog/veritut.html | Verilog tutorial ]] | ||
+ | * [[ http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/ | Verilog on-line tutorial at University of Edinburgh ]] | ||
+ | * [[ http://www.ece.umd.edu/courses/enee359a/verilog_tutorial.pdf | Verilog on-line tutorial at University of Marylin ]] | ||
+ | * [[ http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf | The Verilog Golden Reference Guide ]] | ||
+ | * [[ http://asic.co.in/Index_files/verilogexamples.htm | Code examples ]] | ||
+ | |||
+ | [[http://www.utdallas.edu/~kinchit.desai/index_files/verilog/default.htm]] | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | ====== Overview of HDL simulators ====== | ||
+ | |||
+ | [[http://en.wikipedia.org/wiki/List_of_HDL_simulators]] | ||
+ | |||
+ | [[http://www.asic-world.com/verilog/tools.html]] | ||
+ | |||
+ | |||
+ | Used in the WorkBook: Cadence Incisive environment, Xilinx ISE and ModelSim | ||
+ | |||
+ | |||
+ | ====== Testbench generation ====== | ||
+ | |||
+ | Nice website: | ||
+ | |||
+ | [[http://www.testbench.in/]] | ||
+ | |||
+ | |||
+ | ====== Cadence Incisive tutorial ====== | ||
+ | |||
+ | Tutorial provided with the Cadence Incisive installation: | ||
+ | |||
+ | ''<install dir>/doc/iustutorial/iustutorial.pdf'' | ||
+ | |||
+ | |||
+ | Copy all necessary files in your local working area: | ||
+ | |||
+ | <code> | ||
+ | mkdir iustutorial | ||
+ | cd iustutorial | ||
+ | cp -r <install dir>/doc/iustutorial/examples/files . | ||
+ | </code> | ||
+ | |||
+ | ====== ====== | ||
====== ====== | ====== ====== |