Licensed softwares

Contents

This chapter provides a general overview about which tools for analog, mixed-mode and digital IC design are available at the University of Turin and what are they for. The purpose is not to provide a detailed study of each tool, but rather a short description of the main components and features of the various design platforms, encouraging each user to find out more about the tools required in the daily research work.

Front-end chips for particle detectors are in general mixed-mode systems, which incorporate on the same silicon substrate both analog and digital circuits. CMOS technologies. integrated circuits (ICs) The design of an IC is a multi-step process which starts with schematics simulations and ends-up with laboratory tests. Due to the huge complexity the design of such Application Specific ICs (ASICs) necessary requires computer-aided design (CAD) techniques. In particular electronic design automation (EDA) tools which are de facto an industry standard for IC design. Actually EDA softwares consists of tens of different tools, typically grouped into different design platforms or packages.

Professional EDA softwares are commercial and different software companies offer such kind of tools. The most part of the design platforms licensed by INFN for the VLSI laboratory comes from Cadence Design Systems, which is at present the world largest EDA software and engineering services company for IC and PCB design. A few other tools come from Mentor Graphics and Synopsys.
These tools are completely general and can support different fabrication technologies. When a particular technology is selected a set of configuration and technology-related files is integrated in the design environment. This set of files is commonly referred to as process design kit (PDK).

Tools, licenses and PDKs are provided by an external IC fabrication service. In particular, INFN takes advantage of the software services offered by Europractice. The chip production (submission) is supported by the same fabrication service as well. PDK source, which can be the manufacturer itself or a third part like Europractice and Mosis IC fabrication services or CERN.

Cadence is one of the most complicated packages many of you will ever use. It has options and many different way of accomplishing the same objective.

Modern industrial integrated-circuit-design, CAD tools

analysis of a circuit is the process by which you start with a circuit and you find its properties. An important characteristc of the analysis process is that solutions and propeties are unique. On the other hand, the syntesis or design of a circuit is a process by which you start with a desired set of specifications and you find a circuit that satisfies them. Most important, in a design problem the solution is not unique.

Modern day Integrated Circuit (IC) design is split up into front-end design and back-end design or physical design.

using HDL's, Verification and

The differences between analog and digital design are important.

front-end digital design (logic design and verification) and back-end design (place-and-route, delay calculation, timing analysis etc.)

System Design and Verification

Functional Verification

Logic Design

Digital Implementation (Encounter Digital Implementation System)

Custom IC Design

RF Design

PCB Design

Cadence tools for analog and mixed-mode IC design

tools for digital and mixed-mode IC design

This section introduces different Cadence circuit design tools available.

tools for analog and mixed-mode design and tools for digital and mixed-mode design

VLSI collection of EDA softwares

This platform provides a unified front-to-back design environment. The front-end design environment consists of the Virtuoso schematic editor (VSE) and Virtuoso analog design environment (ADE) product families. The back-end consists of the Virtuoso layout suite (VLS) product family.

Tools: Virtuoso, RC, EDI, SOC, Assura, Spectre, AMS e APS sotto MMSIM package

all the tools you'll need to develop your software are installed and set up

you can start work almost immediately

Tools: cadence, synopsis, mentor

is the directory that contains the software

Analog design flow and required tools

Dia ⇒ Design Rule Checker (DRC), Layout Versus Schematic (LVS) Verifier, Parasitic Extractor (PEX)


A detailed list of most commonly used EDA tools for full custom IC design can be found at
http://pdk101.com/EDA_related/EDA_prime.html


Complete and detailed overview of almost all Cadence tools can be found in

http://tucs.fi/publications/attachment.php?fname=TR831.pdf

bottom-up design approach, starting from the transistor level

The task of designing an analog integrated circuit includes many different steps and the designer is responsible for all these steps except for fabrication.

The first step in the analog design flow of course is the definition of the design specifications, requirements, what we want the circuit to do.


Schematic entry
Once a first schematic view of the circuit is created and the designer This is called schematic entry or schematic capture phase.

Hence a schematic editor tool is required, which offers drawing and visualization capabilities Bear in mind that 'schematic' is a miningless word for a computer, just a human graphical visualization of the circuit!

Besides standard instances, you can also use description behavioral models in terms of hardware description languages (HDLs), such as Verilog-A and Verilog-AMS.

The actual description of a circuit in terms of instances, nets, pins etc. is a plain text file called netlist. As a matter of fact, you can always use a plain text input netlist to define your schematic.


Pre-layout simulations
After the circuit design has been captured in a schematic view, the next step is to simulate the circuit to predict features, performances and issues of the circuit. These are called pre-layout simulatios or schematic-level simulations. This step requires the usage of a circuit simulation tool, simply called simulator. Different circuit simulators can be employed.

At this point the designer may iterate schematic entry and schematic simulations to improve circuit performances until the circuit specifications are fulfilled in simulations. Comparison between simulation results and initial design specifications.


Layout design
Once the schematic satisfies required circuit specifications, the designer can address the next step in the design flow, which is layout design.

The geometrical description of a circuit typically consists of a certain computer database of variously shaped rectangles or polygons (in the x-y plane) at different vertical levels (in the z direction).

Here a layout editor tool is required,

geometrical description of the circuit.


Physical verification
At first, your layout might be required to fit some area constraints defined in the initial specifications. Furthermore, a layout must verify specific geometric rules depending on the technology known as design rules. For enforcing it a Design Rule Check (DRC). Optionally, some electrical errors (e.g. shorts) can be detected with an Electrical Rule Check (ERC). Furthermore, a layout must be compared to the circuit schematic with a Layout-versus-Schematic (LVS) check.

All these steps require the usage of a physical verification tool.

Diva/Dracula/Assura (Cadence), Calibre (Mentor) Hercules (Synopsys)


Post-layout simulations
Once the layout is finished, it is necessary to include Simulations including the geometrical parasitics.

an netlist including all layout parasitics must be extracted and a final simulation of this extracted netlist should be done. This is called a post-layout simulation and is performed with the same simulation tools used to perform pre-layout simulations.


Fabrication
Once verified the layout functionality the final layout is converted to a certain standard file format depending on the founfry using a specic conversion tool.

Graphic Database System II (GDSII)

The fabrication step is not under the designer control.

Waiting for chip back from the foundry, the designer might continue to explore physical verification and post-layout simulations to document expected possible failures as features.


Testing and measurements
After fabrication, the last step in the design flow is determining wheter the fabricated chip meets the initial dedsign specifications with experimental tests and measurements in laboratory.

Cadence Design Framework II (DFII) consists of Cadence tools for design management (Library Manager), schematic entry (Virtuoso Schematics), physical layout (Virtuoso Layout), verification(Assura), and simulation (Spectre).

a tiered architecture (L/Xl/GXL), se viene checked-out a higher license automaticamente sono licenziati anche i tools inferiori

della Mentor Graphics c'e' Calibre layout verification tool, perfettamente integrato il Cadence….

Calibre

IMPORTANTE!!!!!!!!!!!!!!

Assura (Assura Physical Verification ) di per se' fa solo DRC e LVS!!!!!!!!!!!!!!!! La pex quella che si chiama Assura QRC in realta' e' fatta da un altro package, che si chiama Cadence QRC Extraction (che di fatto e' il sostituto di Assura RCX)!

Infatti sono 2 packages distinti, /usr/cadence/Assura_4.10oa-615 e /usr/cadence/EXT_9.13

top-down approach, opposite to the bottom-up used in analog design.

front-end digital design (logic design and verification) back-end design (place-and-route, delay calculation, timing analysis etc.)

design of a digital design system using an automated design environment,

As in analog design flow, the digital design flow begins with design specifications at various levels of abstraction and ends with a layout The design flow begins with specification of the design at various levels of abstraction

automatic hardware generation tools


HDL coding
The design entry phase a design is specified as a mixture of hardware desciption language (HDL)

The two most popular hardware description languages for digital design are Verilog and VHDL.


Functional verification
The designer is also responsible for generating testbenches for logic verification with pre-synthesis simulations


Synthesis
Synthesis is the process of automatic hardware generation from a design description in terms of a hardware description language

This step requires the usage of a synthesis tool

to translate into actual hardware generating the layout with a place-and-route tool


Post-synthesis simulations
After synthesis has been done, the synthesis tool generates a complete list of target hardware components and their timings, wiring delays.

Due to delays of gates and wires, it is possible that the design behavior in post-synthesis simulations are different with respect to pre-synthesis simulations.


Floorplanning


Hardware generation

place-and-route (P&R)

placing components and routing them

layout for a custom IC or into a programmable logic device (PLD) or a field-programmable gate array (FPGA)


Physical verification
layout DRC, LVS


Fabrication
integration with analog part


Testing and measurements

Incisive functional verification platform The Cadence Incisive Unified Simulator (IUS) Verilog, VHDL, SystemC, System Verilog, etc.

della Synopsys c'e' Verilog Compiler Simulator (VCS)

Cadence RC (RTL Compiler), Cadence EDI (Encounter Digital Implementation)

Della Synopsis abbiamo Verilog Simulator Compiler (VSC)

Testing and measurements

After fabrication, the last step in the design flow is determining wheter the fabricated chip meets the initial dedsign specifications with experimental tests and measurements in laboratory.

Printed Circuit Board (PCB)

Typically a chip is wire-bonded onto a mezzanine card, which provides mechanical support, power and output test points. Mezzanine is then plugged onto a test PCB equipped with

commercial discrete componets, trimmers and further output test points.

test PCB for testing and measurements

create a schematic view of the board, placing components and connecting them with wires.

Once you have the schematic, you have to generate the netlist and import it to Allegro PCB Editor to complete the board layout. You place the components, define power and ground planes, route physical wires using this tool. Finally you must verify the board for errors.

floorplanning, place-and-route

For PCB design, INFN licenses for the VLSI laboratory the industry-standard Cadence Allegro SPB (Silicon Package Board) 16.x. The latest available software release is 16.5.

All design platforms, technologies, licenses and configuration files are physically installed on a single server machine (elt59xl). Symbolic links placed in the /usr directory of client machines allow users to access the different software resources.

/export/elt59xl/disk0/

/export/elt59xl/disk0/cadence

/export/elt59xl/disk0/mentor

/export/elt59xl/disk0/synopsis

ls -l /usr
ln -s  /usr/cadence



Last update: Luca Pacher - Mar 5, 2013

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