Power consumption evaluation in Cadence Virtuoso

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example using a simple CMOS inverter testbench (P = 1/2CV^2 Vdd is a well known result)

Pavg = VDD x Iavg

VAR("Vdd")*average(IT("/Mx/D"))

create a CMOS inverter schematic as described in the CMOS inverter tutorial

ADE L ⇒ Outputs ⇒ Save All..



Last update: Luca Pacher - Apr 23, 2013

  • vlsi/workbook/analog/simref/power.txt
  • Ultima modifica: 22/08/2013 19:59
  • da pacher