Differenze
Queste sono le differenze tra la revisione selezionata e la versione attuale della pagina.
| Entrambe le parti precedenti la revisione Revisione precedente Prossima revisione | Revisione precedente | ||
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vlsi:workbook2:sdc [05/06/2014 23:44] pacher |
vlsi:workbook2:sdc [05/06/2014 23:45] (versione attuale) pacher |
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| Linea 7: | Linea 7: | ||
| - | Reference documentation: | + | Reference documentation from Synopsys: |
| //Synopsys Timing Constraints and Optimization User Guide// (''tcoug.pdf'') \\ | //Synopsys Timing Constraints and Optimization User Guide// (''tcoug.pdf'') \\ | ||
| Linea 16: | Linea 16: | ||
| - | //Setting Constraints and Performing Timing Analysis Using Encounter RTL Compiler// (''rc_ta.pdf'') | + | Documentation from Cadence: |
| + | //Setting Constraints and Performing Timing Analysis Using Encounter RTL Compiler// (''rc_ta.pdf'') \\ | ||
| ''<install dir>/doc/rc_ta/rc_ta.pdf'' | ''<install dir>/doc/rc_ta/rc_ta.pdf'' | ||
| - | + | Useful external links: | |
| - | + | ||
| [[http://www.vlsi-expert.com/2011/02/synopsys-design-constraints-sdc-basics.html]] | [[http://www.vlsi-expert.com/2011/02/synopsys-design-constraints-sdc-basics.html]] | ||