Differenze
Queste sono le differenze tra la revisione selezionata e la versione attuale della pagina.
| Entrambe le parti precedenti la revisione Revisione precedente Prossima revisione | Revisione precedente Prossima revisione Entrambe le parti successive la revisione | ||
|
vlsi:workbook2:sdc [05/06/2014 17:23] pacher |
vlsi:workbook2:sdc [05/06/2014 17:34] pacher |
||
|---|---|---|---|
| Linea 5: | Linea 5: | ||
| - | [[http://www.synopsys.com/Community/Interoperability/Pages/TapinSDC.aspx]] | ||
| - | [[http://www.vlsi-expert.com/2011/02/synopsys-design-constraints-sdc-basics.html]] | ||
| + | //Synopsys Timing Constraints and Optimization User Guide// \\ | ||
| + | [[http://acms.ucsd.edu/_files/tcoug.pdf]] | ||
| - | [[http://www.microsemi.com/document-portal/doc_download/131597-design-constraints-guide]] | + | [[http://www.synopsys.com/Community/Interoperability/Pages/TapinSDC.aspx]] |
| + | [[http://www.vlsi-expert.com/2011/02/synopsys-design-constraints-sdc-basics.html]] | ||
| + | [[http://www.microsemi.com/document-portal/doc_download/131597-design-constraints-guide]] | ||
| + | [[http://application-notes.digchip.com/056/56-39741.pdf]] | ||
| ====== ====== | ====== ====== | ||