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vlsi:workbook:digital [23/11/2013 17:54] panati |
vlsi:workbook:digital [24/11/2013 19:39] panati |
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* **[[vlsi:workbook:digital:hdlsim|Verilog/VHDL simulation]]** | * **[[vlsi:workbook:digital:hdlsim|Verilog/VHDL simulation]]** | ||
* [[vlsi:workbook:digital:hdlsim#introduction|Introduction]] | * [[vlsi:workbook:digital:hdlsim#introduction|Introduction]] | ||
- | * ... | + | * [[vlsi:workbook:digital:hdlsim#build_your_own_cadence_incisive_documentation_repository|Build your own Cadence Incisive documentation repository]] |
- | * [[vlsi:workbook:digital:hdlsim:verilog_tutorials|Verilog/VHDL simulation examples]] | + | * [[vlsi:workbook:digital:hdlsim#Verilog/VHDL_references_and_documentation|Verilog/VHDL references and documentation]] |
- | * [[vlsi:workbook:digital:hdlsim:vhdl_tutorials|VHDL simulation examples]] | + | * [[vlsi:workbook:digital:hdlsim:verilog_tutorials|Verilog simulation tutorials]] |
+ | * [[vlsi:workbook:digital:hdlsim:vhdl_tutorials|VHDL simulation tutorials]] | ||
* ... | * ... | ||
* **[[vlsi:workbook:digital:syn|Digital synthesis]]** | * **[[vlsi:workbook:digital:syn|Digital synthesis]]** | ||
- | * Introduction | + | * [[vlsi:workbook:digital:syn#introduction|Introduction]] |
- | * Tools overview | + | * [[vlsi:workbook:digital:syn#Getting_started_with_cadence_RTL_compiler_(RC)|Getting started with Cadence RTL Compiler (RC)]] |
- | * Reference documentation | + | |
* [[vlsi:workbook:digital:syn:power|Power Analysis]] | * [[vlsi:workbook:digital:syn:power|Power Analysis]] | ||
+ | * [[vlsi:private:workbook:digital:syn:tutorials:verilog_digital_synthesis_tutorials|Verilog Digital synthesis tutorials]] | ||
+ | * [[vlsi:private:workbook:digital:syn:tutorials:vhdl_digital_synthesis_tutorials|VHDL Digital synthesis tutorials]] | ||
* ... | * ... | ||
- | * [[vlsi:private:workbook:digital:syn:tutorials|Digital synthesis tutorials]] | ||
* **[[vlsi:workbook:digital:lec|Logic equivalence checking (LEC)]]** | * **[[vlsi:workbook:digital:lec|Logic equivalence checking (LEC)]]** | ||
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* Tools overview | * Tools overview | ||
* Reference documentation | * Reference documentation | ||
- | * [[vlsi:private:workbook:digital:pnr:tutorials|Place and route tutorials]] | + | * [[vlsi:private:workbook:digital:pnr:tutorials:verilog_pnr_tutorials|Verilog Place and Route tutorials]] |
+ | * [[vlsi:private:workbook:digital:pnr:tutorials:VHDL_pnr_tutorials|VHDL Place and Route tutorials]] | ||
* [[vlsi:workbook:digital:pnr:power|Power Analysis]] | * [[vlsi:workbook:digital:pnr:power|Power Analysis]] | ||
* [[vlsi:workbook:digital:pnr:gdsII|Importing gdsII in Virtuoso]] | * [[vlsi:workbook:digital:pnr:gdsII|Importing gdsII in Virtuoso]] |