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vlsi:workbook:digital:hdlsim [23/11/2013 22:33] panati |
vlsi:workbook:digital:hdlsim [22/04/2014 02:29] pacher |
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* [[vlsi:workbook:digital:hdlsim#build_your_own_cadence_incisive_documentation_repository|Build your own Cadence Incisive documentation repository]] | * [[vlsi:workbook:digital:hdlsim#build_your_own_cadence_incisive_documentation_repository|Build your own Cadence Incisive documentation repository]] | ||
* [[vlsi:workbook:digital:hdlsim#Verilog/VHDL_references_and_documentation|Verilog/VHDL references and documentation]] | * [[vlsi:workbook:digital:hdlsim#Verilog/VHDL_references_and_documentation|Verilog/VHDL references and documentation]] | ||
- | * [[vlsi:workbook:digital:hdlsim:verilog_tutorials|Verilog simulation examples]] | + | * [[vlsi:workbook:digital:hdlsim:verilog_tutorials|Verilog simulation tutorials]] |
- | * [[vlsi:workbook:digital:hdlsim:vhdl_tutorials|VHDL simulation examples]] | + | * [[vlsi:workbook:digital:hdlsim:vhdl_tutorials|VHDL simulation tutorials]] |
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* [[ http://asic.co.in/Index_files/verilogexamples.htm | Code examples ]] | * [[ http://asic.co.in/Index_files/verilogexamples.htm | Code examples ]] | ||
+ | [[http://www.utdallas.edu/~kinchit.desai/index_files/verilog/default.htm]] | ||
+ | |||
+ | |||
+ | ====== Overview of HDL simulators ====== | ||
+ | |||
+ | [[http://en.wikipedia.org/wiki/List_of_HDL_simulators]] | ||
+ | |||
+ | [[http://www.asic-world.com/verilog/tools.html]] | ||
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+ | |||
+ | Used in the WorkBook: Cadence Incisive environment, Xilinx ISE and ModelSim | ||
+ | |||
+ | |||
+ | ====== Testbench generation ====== | ||
+ | |||
+ | Nice website: | ||
+ | |||
+ | [[http://www.testbench.in/]] | ||
+ | |||
+ | |||
+ | |||
+ | ====== ====== | ||
+ | |||
+ | ====== ====== | ||
+ | \\ | ||
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Last update: [[panati@NOSPAMto.infn.it|Serena Panati]] - Sep 19th, 2013 | Last update: [[panati@NOSPAMto.infn.it|Serena Panati]] - Sep 19th, 2013 | ||
~~NOTOC~~ | ~~NOTOC~~ |