Differenze

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-====== Reference documentation for VHDL/Verilog Simulations ======
-===== Verilog/VHDL references and documentation =====
-I tutorial forniscono gia' il codice Verilog/VHDL, quindi uno puo' anche non saperlo!
-Alcune referenze on-line sono:
-  * [[http://esd.cs.ucr.edu/labs/tutorial/|VHDL Tutorial: Learn by Example]]
-  * [[ http://asic.co.in/Index_files/tutorials/VHDL_Tutorial.htm | qua c'e' di tutto! ]]
-  * [[ http://en.wikipedia.org/wiki/VHDL | VHDL from Wikipedia]]
-  * [[ http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html | VHDL primer ]]
-  * [[ http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf | The VHDL Cookbook ]]
-  * [[ http://en.wikipedia.org/wiki/Verilog | Verilog from Wikipedia ]]
-  * [[ http://www.asic-world.com/verilog/veritut.html | Verilog tutorial ]]
-  * [[ http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/ | Verilog on-line tutorial at University of Edinburgh ]]
-  * [[ http://www.ece.umd.edu/courses/enee359a/verilog_tutorial.pdf | Verilog on-line tutorial at University of Marylin ]]
-  * [[ http://www.fpga.com.cn/hdl/training/verilog%20reference%20guide.pdf | The Verilog Golden Reference Guide ]]
-  * [[ http://asic.co.in/Index_files/verilogexamples.htm | Code examples ]]