Differenze

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--- vlsi:resources:systemverilog [02/07/2015 22:48]
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+++ vlsi:resources:systemverilog [14/07/2015 10:21]
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-====== SystemVerilog ======
+====== SystemVerilog references ======
+[ __[[vlsi:home|Home]]__ ]
+[ __[[vlsi:workbook|Design WorkBook]]__ ]
+[ __[[vlsi:resources:books|Books]]__ ]
+//IEEE std 1800-2012//  \\
+[[http://www.eda.org/sv/SystemVerilog_3.1a.pdf|SystemVerilog 3.1a Language Reference Manual]]
+//OVM/UVM User's Guide//
+**Syntax highlighting for the Gedit text editor**
+**1.** make a copy of the Verilog language style
+''/usr/share/gtksourceview-2.0/language-specs/verilog.lang''
+**2.** add new SystemVerilog reserved words with the XML syntax
+<code>
+<keyword>word</keyword>
+</code>