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SystemVerilog references
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IEEE std 1800-2012
SystemVerilog 3.1a Language Reference Manual
OVM/UVM User's Guide
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1. make a copy of the Verilog language style
/usr/share/gtksourceview-2.0/language-specs/verilog.lang
2. add new SystemVerilog reserved words with the XML syntax
<keyword>word</keyword>