SystemVerilog references

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IEEE std 1800-2012
SystemVerilog 3.1a Language Reference Manual

OVM/UVM User's Guide

Syntax highlighting for the Gedit text editor

1. make a copy of the Verilog language style


2. modify the language id as

<language id="systemverilog" _name="SystemVerilog" version="2.0" _section="Sources">


   <context id="systemverilog">      <!-- modified from verilog to systemverilog -->
        <context ref="line-comment"/>
        <context ref="block-comment"/>
        <context ref="close-comment-outside-comment"/>
        <context ref="compiler-directive"/>
        <context ref="keywords"/>
        <context ref="gates"/>
        <context ref="types"/>
        <context ref="binary-number"/>
        <context ref="octal-number"/>
        <context ref="decimal-number"/>
        <context ref="hexadecimal-number"/>

3. change the default file extension

<property name="globs">*.sv</property> 

4. add new SystemVerilog reserved words by following the XML syntax