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--- vlsi:workbook2:makefiles [30/05/2014 18:47]
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+++ vlsi:workbook2:makefiles [05/06/2014 23:27] (versione attuale)
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@@ Linea 20: / Linea 20: @@
 [[http://www.csee.umbc.edu/portal/help/VHDL/Makefile.cadence]]
+[[http://www.ece.ucdavis.edu/~astill/Makefile]]
 ====== Makefile for Cadence Incisive tools ======
+[[http://vak-opensource.googlecode.com/svn/trunk/hardware/systemverilog/uart-example/Makefile]] \\
+[[https://groups.google.com/forum/#!topic/comp.lang.verilog/iMd4NMmko8s]]
 ''configure'' file:
@@ Linea 350: / Linea 354: @@
 ====== Makefile for Cadence RTL Compiler (RC) ======
+[[http://people.virginia.edu/~ll2bf/docs/various/flow_example.html]]  \\
+[[http://soc.eurecom.fr/EDC/cadence_rc_quick_start/src/Makefile]]
 <code>
@@ Linea 357: / Linea 364: @@
 # RTL Compiler executable
 RC = rc
+RM = rm -f
 # RTL Compiler command line options
@@ Linea 368: / Linea 377: @@
 # Target: syn
 # call Cadence RTL Compiler with input main Tcl script
-syn:
+syn: clean
         $(RC) $(RCOPTS)
@@ Linea 375: / Linea 384: @@
 # delete all log and backup files
 clean:
-      	find ./ -name '*.log*'     -exec rm -f {} \;
+      	@find ./ -name '*.log*'     -exec $(RM) {} \;
-        find ./ -name '*~'         -exec rm -f {} \;
+        @find ./ -name '*.cmd*'     -exec $(RM) {} \;
+        @find ./ -name '*~'         -exec $(RM) {} \;
 </code>