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Verilog/VHDL simulations with Xilinx ISE Simulator (ISim)
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Contents
- Introduction
- Documentation
- Tutorials
Introduction
http://www.xilinx.com/tools/isim.htm
http://www.rte.se/blog/blogg-modesty-corex/isim-hdl-simulator
http://vhdlguru.blogspot.it/2010/12/tips-for-running-successful-simulation.html
Documentation
ISim User Guide
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/plugin_ism.pdf
ISim In-Depth Tutorial
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug682.pdf
UNIX environment setup
linux% source /opt/edatools/xilinx/ISE14.6/settings.csh
or write your own setup script by including:
# ISE installation directory setenv ISE_DIR /opt/edatools/xilinx/ISE14.6/ISE setenv XILINX $ISE_DIR # add Xilinx executables to search path set path = ( $ISE_DIR/bin/lin $ISE_DIR/sysgen/util $path )
Makefile
# HDL sources (project file)
SOURCES = design.prj
# top-level design unit (testbench)
TOP = tb_design
# local library mapping file
LIBFILE = libs.ini
# ISim compiler/elaborator
CC = fuse
# output simulation executable
SIMEXE = $(TOP).exe
# compiler/elaborator options
CCFLAGS = -initfile $(LIBFILE) \
-incremental \
-verbose 0 \
-prj $(SOURCES) \
-out $(SIMEXE)
SIMFLAGS = -gui \
-wdb ./results/wdb/$(TOP).wdb \
-tclbatch ./scripts/run.tcl
# useful command alias
RM = rm
RMDIR = rm -rf
all:
$(CC) $(CCFLAGS) work.$(TOP)
sim:
./$(SIMEXE) $(SIMFLAGS) &
clean:
@find ./ -name '*.log' -exec $(RM) {} \;
@find ./ -name '*.cmd' -exec $(RM) {} \;
@find ./ -name '*.xmsgs' -exec $(RM) {} \;
@find ./ -name '*~' -exec $(RM) {} \;
@find ./ -name '*.exe' -exec $(RM) {} \;
@$(RMDIR) isim/
Run the Xilinx ISE In-Depth Tutorial
cd ~/scratch/xilinx mkdir projects
cd ~/scratch/xilinx/projects ise &