Differenze
Queste sono le differenze tra la revisione selezionata e la versione attuale della pagina.
Entrambe le parti precedenti la revisione Revisione precedente Prossima revisione | Revisione precedente | ||
vlsi:workbook:digital [18/03/2014 20:16] pacher |
vlsi:workbook:digital [12/06/2014 19:26] (versione attuale) pacher |
||
---|---|---|---|
Linea 18: | Linea 18: | ||
+ | Goal (in a wonderful world): **build a standard cell library from scratch** | ||
+ | with simple SPICE models, extract liberty description of standard cells, create dummy layouts and | ||
+ | abstract up to place-and-route !!! Everything... **technology-independent** !!! | ||
+ | |||
+ | Static timing analysis: \\ | ||
+ | [[http://en.m.wikipedia.org/wiki/Static_timing_analysis]] | ||
Linea 48: | Linea 54: | ||
* [[vlsi:workbook:digital:hdlsim:vhdl_tutorials|VHDL simulation tutorials]] | * [[vlsi:workbook:digital:hdlsim:vhdl_tutorials|VHDL simulation tutorials]] | ||
* ... | * ... | ||
+ | |||
+ | |||
+ | * **[[vlsi:workbook:digital:stdcells|Build a standard cell library from scratch]]** | ||
+ | * Introduction | ||
+ | * ... | ||
+ | * ... | ||
+ | |||
+ | |||
* **[[vlsi:workbook:digital:syn|Digital synthesis]]** | * **[[vlsi:workbook:digital:syn|Digital synthesis]]** | ||
* [[vlsi:workbook:digital:syn#introduction|Introduction]] | * [[vlsi:workbook:digital:syn#introduction|Introduction]] | ||
- | * [[vlsi:workbook:digital:syn#Getting_started_with_cadence_RTL_compiler_(RC)|Getting started with Cadence RTL Compiler (RC)]] | + | * [[vlsi:workbook:digital:syn#getting_started_with_cadence_RTL_compiler|Getting started with Cadence RTL Compiler]] |
* [[vlsi:workbook:digital:syn:power|Power Analysis]] | * [[vlsi:workbook:digital:syn:power|Power Analysis]] | ||
* [[vlsi:private:workbook:digital:syn:tutorials:verilog_digital_synthesis_tutorials|Verilog Digital synthesis tutorials]] | * [[vlsi:private:workbook:digital:syn:tutorials:verilog_digital_synthesis_tutorials|Verilog Digital synthesis tutorials]] |