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vlsi:workbook:digital [14/01/2014 18:46]
pacher 		vlsi:workbook:digital [12/06/2014 19:26] (versione attuale)
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 [ __[[vlsi:​workbook:​digital:​howtos|HowTo'​s]]__ ] [ __[[vlsi:​workbook:​digital:​howtos|HowTo'​s]]__ ]
 [ __[[vlsi:​workbook:​digital:​faqs|FAQs]]__ ] [ __[[vlsi:​workbook:​digital:​faqs|FAQs]]__ ]
 +[ __[[vlsi:​workbook:​digital:​tmp|/​tmp]]__ ]
 +
  
 \\ \\
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 +Goal (in a wonderful world): **build a standard cell library from scratch** ​
 +with simple SPICE models, extract liberty description of standard cells, create dummy layouts and 
 +abstract up to place-and-route !!! Everything... **technology-independent** !!!
 +
 +Static timing analysis: ​ \\
 +[[http://​en.m.wikipedia.org/​wiki/​Static_timing_analysis]]
  
  
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       * [[vlsi:​workbook:​digital:​hdlsim:​vhdl_tutorials|VHDL simulation tutorials]]       * [[vlsi:​workbook:​digital:​hdlsim:​vhdl_tutorials|VHDL simulation tutorials]]
       * ...       * ...
 +
 + 
 +   * **[[vlsi:​workbook:​digital:​stdcells|Build a standard cell library from scratch]]**
 +      * Introduction
 +      * ...
 +      * ...
 +
 +
  
    * **[[vlsi:​workbook:​digital:​syn|Digital synthesis]]**    * **[[vlsi:​workbook:​digital:​syn|Digital synthesis]]**
       * [[vlsi:​workbook:​digital:​syn#​introduction|Introduction]]       * [[vlsi:​workbook:​digital:​syn#​introduction|Introduction]]
-      * [[vlsi:​workbook:​digital:​syn#​Getting_started_with_cadence_RTL_compiler_(RC)|Getting started with Cadence RTL Compiler ​(RC)]]+      * [[vlsi:​workbook:​digital:​syn#​getting_started_with_cadence_RTL_compiler|Getting started with Cadence RTL Compiler]]
       * [[vlsi:​workbook:​digital:​syn:​power|Power Analysis]]       * [[vlsi:​workbook:​digital:​syn:​power|Power Analysis]]
       * [[vlsi:​private:​workbook:​digital:​syn:​tutorials:​verilog_digital_synthesis_tutorials|Verilog Digital synthesis tutorials]]       * [[vlsi:​private:​workbook:​digital:​syn:​tutorials:​verilog_digital_synthesis_tutorials|Verilog Digital synthesis tutorials]]