Differenze
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| [ __[[vlsi:home|Home]]__ ] | [ __[[vlsi:home|Home]]__ ] | ||
| + | [ __[[vlsi:workbook|Back]]__ ] | ||
| [ __[[vlsi:workbook|Design WorkBook]]__ ] | [ __[[vlsi:workbook|Design WorkBook]]__ ] | ||
| [ __[[vlsi:workbook:digital#contents|Contents]]__ ] | [ __[[vlsi:workbook:digital#contents|Contents]]__ ] | ||
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| [ __[[vlsi:workbook:digital:howtos|HowTo's]]__ ] | [ __[[vlsi:workbook:digital:howtos|HowTo's]]__ ] | ||
| [ __[[vlsi:workbook:digital:faqs|FAQs]]__ ] | [ __[[vlsi:workbook:digital:faqs|FAQs]]__ ] | ||
| + | [ __[[vlsi:workbook:digital:tmp|/tmp]]__ ] | ||
| + | |||
| \\ | \\ | ||
| The third part of the WorkBook is dedicated to **digital IC design**... | The third part of the WorkBook is dedicated to **digital IC design**... | ||
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| + | |||
| + | Goal (in a wonderful world): **build a standard cell library from scratch** | ||
| + | with simple SPICE models, extract liberty description of standard cells, create dummy layouts and | ||
| + | abstract up to place-and-route !!! Everything... **technology-independent** !!! | ||
| + | |||
| + | Static timing analysis: \\ | ||
| + | [[http://en.m.wikipedia.org/wiki/Static_timing_analysis]] | ||
| + | |||
| == Contents == | == Contents == | ||
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| * .... | * .... | ||
| * .... | * .... | ||
| + | |||
| + | |||
| + | * **[[vlsi:workbook:digital:cmos_logic|Basic digital CMOS ]]** | ||
| + | * Introduction | ||
| + | * .... | ||
| + | * .... | ||
| + | |||
| * **[[vlsi:workbook:digital:hdlsim|Verilog/VHDL simulation]]** | * **[[vlsi:workbook:digital:hdlsim|Verilog/VHDL simulation]]** | ||
| + | * [[vlsi:workbook:digital:hdlsim#introduction|Introduction]] | ||
| + | * [[vlsi:workbook:digital:hdlsim#build_your_own_cadence_incisive_documentation_repository|Build your own Cadence Incisive documentation repository]] | ||
| + | * [[vlsi:workbook:digital:hdlsim#Verilog/VHDL_references_and_documentation|Verilog/VHDL references and documentation]] | ||
| + | * [[vlsi:workbook:digital:hdlsim:verilog_tutorials|Verilog simulation tutorials]] | ||
| + | * [[vlsi:workbook:digital:hdlsim:vhdl_tutorials|VHDL simulation tutorials]] | ||
| + | * ... | ||
| + | |||
| + | |||
| + | * **[[vlsi:workbook:digital:stdcells|Build a standard cell library from scratch]]** | ||
| * Introduction | * Introduction | ||
| - | * Tools overview | ||
| - | * Reference documentation | ||
| * ... | * ... | ||
| - | * [[vlsi:workbook:digital:hdlsim:tutorials|Verilog/VHDL simulation examples]] | + | * ... |
| + | |||
| * **[[vlsi:workbook:digital:syn|Digital synthesis]]** | * **[[vlsi:workbook:digital:syn|Digital synthesis]]** | ||
| - | * Introduction | + | * [[vlsi:workbook:digital:syn#introduction|Introduction]] |
| - | * Tools overview | + | * [[vlsi:workbook:digital:syn#getting_started_with_cadence_RTL_compiler|Getting started with Cadence RTL Compiler]] |
| - | * Reference documentation | + | |
| * [[vlsi:workbook:digital:syn:power|Power Analysis]] | * [[vlsi:workbook:digital:syn:power|Power Analysis]] | ||
| + | * [[vlsi:private:workbook:digital:syn:tutorials:verilog_digital_synthesis_tutorials|Verilog Digital synthesis tutorials]] | ||
| + | * [[vlsi:private:workbook:digital:syn:tutorials:vhdl_digital_synthesis_tutorials|VHDL Digital synthesis tutorials]] | ||
| * ... | * ... | ||
| - | * [[vlsi:workbook:digital:syn:tutorials|Digital synthesis tutorials]] | ||
| * **[[vlsi:workbook:digital:lec|Logic equivalence checking (LEC)]]** | * **[[vlsi:workbook:digital:lec|Logic equivalence checking (LEC)]]** | ||
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| * ... | * ... | ||
| - | * **[[vlsi:workbook:digital:pnr|Place and route (PNR)]]** | + | * **[[vlsi:workbook:digital:pnr|Automatic place and route (PNR) with Cadence Encounter]]** |
| * Introduction | * Introduction | ||
| * Tools overview | * Tools overview | ||
| * Reference documentation | * Reference documentation | ||
| + | * [[vlsi:private:workbook:digital:pnr:tutorials:verilog_pnr_tutorials|Verilog Place and Route tutorials]] | ||
| + | * [[vlsi:private:workbook:digital:pnr:tutorials:VHDL_pnr_tutorials|VHDL Place and Route tutorials]] | ||
| + | * [[vlsi:workbook:digital:pnr:power|Power Analysis]] | ||
| + | * [[vlsi:private:workbook:digital:pnr:gdsII|Importing gdsII in Virtuoso]] | ||
| * ... | * ... | ||