Differenze
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vlsi:workbook:digital [24/11/2013 19:44] panati |
vlsi:workbook:digital [18/03/2014 20:16] pacher |
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| [ __[[vlsi:home|Home]]__ ] | [ __[[vlsi:home|Home]]__ ] | ||
| + | [ __[[vlsi:workbook|Back]]__ ] | ||
| [ __[[vlsi:workbook|Design WorkBook]]__ ] | [ __[[vlsi:workbook|Design WorkBook]]__ ] | ||
| [ __[[vlsi:workbook:digital#contents|Contents]]__ ] | [ __[[vlsi:workbook:digital#contents|Contents]]__ ] | ||
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| [ __[[vlsi:workbook:digital:howtos|HowTo's]]__ ] | [ __[[vlsi:workbook:digital:howtos|HowTo's]]__ ] | ||
| [ __[[vlsi:workbook:digital:faqs|FAQs]]__ ] | [ __[[vlsi:workbook:digital:faqs|FAQs]]__ ] | ||
| + | [ __[[vlsi:workbook:digital:tmp|/tmp]]__ ] | ||
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| The third part of the WorkBook is dedicated to **digital IC design**... | The third part of the WorkBook is dedicated to **digital IC design**... | ||
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| == Contents == | == Contents == | ||
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| * .... | * .... | ||
| * .... | * .... | ||
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| + | * **[[vlsi:workbook:digital:cmos_logic|Basic digital CMOS ]]** | ||
| + | * Introduction | ||
| + | * .... | ||
| + | * .... | ||
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| * **[[vlsi:workbook:digital:hdlsim|Verilog/VHDL simulation]]** | * **[[vlsi:workbook:digital:hdlsim|Verilog/VHDL simulation]]** | ||
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| * ... | * ... | ||
| - | * **[[vlsi:workbook:digital:pnr|Place and route (PNR)]]** | + | * **[[vlsi:workbook:digital:pnr|Automatic place and route (PNR) with Cadence Encounter]]** |
| * Introduction | * Introduction | ||
| * Tools overview | * Tools overview | ||