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Entrambe le parti precedenti la revisione Revisione precedente Prossima revisione | Revisione precedente Prossima revisione Entrambe le parti successive la revisione | ||
vlsi:workbook:digital [23/11/2013 23:42] panati |
vlsi:workbook:digital [24/11/2013 19:44] panati |
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* [[vlsi:workbook:digital:syn#Getting_started_with_cadence_RTL_compiler_(RC)|Getting started with Cadence RTL Compiler (RC)]] | * [[vlsi:workbook:digital:syn#Getting_started_with_cadence_RTL_compiler_(RC)|Getting started with Cadence RTL Compiler (RC)]] | ||
* [[vlsi:workbook:digital:syn:power|Power Analysis]] | * [[vlsi:workbook:digital:syn:power|Power Analysis]] | ||
- | * [[vlsi:private:workbook:digital:syn:tutorials#verilog_digital_synthesis_tutorials|Verilog Digital synthesis tutorials]] | + | * [[vlsi:private:workbook:digital:syn:tutorials:verilog_digital_synthesis_tutorials|Verilog Digital synthesis tutorials]] |
- | * [[vlsi:private:workbook:digital:syn:tutorials#vhdl_digital_synthesis_tutorials|VHDL Digital synthesis tutorials]] | + | * [[vlsi:private:workbook:digital:syn:tutorials:vhdl_digital_synthesis_tutorials|VHDL Digital synthesis tutorials]] |
* ... | * ... | ||
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* Tools overview | * Tools overview | ||
* Reference documentation | * Reference documentation | ||
- | * [[vlsi:private:workbook:digital:pnr:tutorials|Place and route tutorials]] | + | * [[vlsi:private:workbook:digital:pnr:tutorials:verilog_pnr_tutorials|Verilog Place and Route tutorials]] |
+ | * [[vlsi:private:workbook:digital:pnr:tutorials:VHDL_pnr_tutorials|VHDL Place and Route tutorials]] | ||
* [[vlsi:workbook:digital:pnr:power|Power Analysis]] | * [[vlsi:workbook:digital:pnr:power|Power Analysis]] | ||
- | * [[vlsi:workbook:digital:pnr:gdsII|Importing gdsII in Virtuoso]] | + | * [[vlsi:private:workbook:digital:pnr:gdsII|Importing gdsII in Virtuoso]] |
* ... | * ... | ||