Differenze
Queste sono le differenze tra la revisione selezionata e la versione attuale della pagina.
Entrambe le parti precedenti la revisione Revisione precedente Prossima revisione | Revisione precedente | ||
vlsi:workbook:digital:syn [22/04/2014 01:29] pacher |
vlsi:workbook:digital:syn [13/06/2014 00:17] (versione attuale) pacher |
||
---|---|---|---|
Linea 19: | Linea 19: | ||
- | ===== Introduction ===== | + | ====== Introduction ====== |
+ | A complete tutorial: | ||
+ | |||
+ | [[http://www.siue.edu/~gengel/ece484LabMaterial/RTLsynthesisTut.pdf]] | ||
===== Getting started with Cadence RTL Compiler (RC) ===== | ===== Getting started with Cadence RTL Compiler (RC) ===== | ||
Linea 89: | Linea 92: | ||
+ | ====== SDC clock definition ====== | ||
+ | |||
+ | <code> | ||
+ | rc:/> dc::create_clock -help | ||
+ | |||
+ | Usage: create_clock [-add] [-name <string>] [-comment <string>] [-domain <string>] -period <float> | ||
+ | [-waveform <float>+] [-apply_inverted <port|pin>+] [<port|pin>+] | ||
+ | |||
+ | [-add]: | ||
+ | should the sources add or overwrite | ||
+ | [-name <string>]: | ||
+ | name of the clock | ||
+ | [-comment <string>]: | ||
+ | comment to be tagged with this command | ||
+ | [-domain <string>]: | ||
+ | name of the clock domain for the clock | ||
+ | -period <float>: | ||
+ | clock period | ||
+ | [-waveform <float>+]: | ||
+ | waveform string | ||
+ | [-apply_inverted <port|pin>+]: | ||
+ | sources of the clock that are inverted | ||
+ | [<port|pin>+]: | ||
+ | sources that are not inverted | ||
+ | </code> | ||
+ | |||
+ | |||
+ | Fo deteiled information use | ||
+ | |||
+ | <code> | ||
+ | rc:/> man dc::create_clock | ||
+ | </code> | ||
+ | |||
+ | |||
+ | |||
+ | <code> | ||
+ | -waveform <f><loat...> Specifies the rise and fall edge times of | ||
+ | the clock waveform over one clock period. The | ||
+ | first value corresponds to the first rising | ||
+ | transition after time zero. The numbers should | ||
+ | represent one full clock period. If you omit this | ||
+ | option, a default waveform is assumed: the leading | ||
+ | edge occurs at 0 and the trailing edge occurs at | ||
+ | the midpoint of the period, such that a symmetric | ||
+ | clock is generated. | ||
+ | </code> | ||
====== Post-synthesis simulation ====== | ====== Post-synthesis simulation ====== |