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[ __[[vlsi:workbook:digital#contents|Back to index]]__ ] | [ __[[vlsi:workbook:digital#contents|Back to index]]__ ] | ||
[ __[[vlsi:workbook:digital:syn#contents|Contents]]__ ] | [ __[[vlsi:workbook:digital:syn#contents|Contents]]__ ] | ||
+ | [ __[[vlsi:workbook:digital:syn:tmp|/tmp]]__ ] | ||
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- | ===== Introduction ===== | + | ====== Introduction ====== |
+ | |||
+ | A complete tutorial: | ||
+ | |||
+ | [[http://www.siue.edu/~gengel/ece484LabMaterial/RTLsynthesisTut.pdf]] | ||
===== Getting started with Cadence RTL Compiler (RC) ===== | ===== Getting started with Cadence RTL Compiler (RC) ===== | ||
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rc:/> source rtl.tcl | rc:/> source rtl.tcl | ||
</code> | </code> | ||
+ | |||
+ | |||
+ | |||
+ | ====== SDC clock definition ====== | ||
+ | |||
+ | <code> | ||
+ | rc:/> dc::create_clock -help | ||
+ | |||
+ | Usage: create_clock [-add] [-name <string>] [-comment <string>] [-domain <string>] -period <float> | ||
+ | [-waveform <float>+] [-apply_inverted <port|pin>+] [<port|pin>+] | ||
+ | |||
+ | [-add]: | ||
+ | should the sources add or overwrite | ||
+ | [-name <string>]: | ||
+ | name of the clock | ||
+ | [-comment <string>]: | ||
+ | comment to be tagged with this command | ||
+ | [-domain <string>]: | ||
+ | name of the clock domain for the clock | ||
+ | -period <float>: | ||
+ | clock period | ||
+ | [-waveform <float>+]: | ||
+ | waveform string | ||
+ | [-apply_inverted <port|pin>+]: | ||
+ | sources of the clock that are inverted | ||
+ | [<port|pin>+]: | ||
+ | sources that are not inverted | ||
+ | </code> | ||
+ | |||
+ | |||
+ | Fo deteiled information use | ||
+ | |||
+ | <code> | ||
+ | rc:/> man dc::create_clock | ||
+ | </code> | ||
+ | |||
+ | |||
+ | |||
+ | <code> | ||
+ | -waveform <f><loat...> Specifies the rise and fall edge times of | ||
+ | the clock waveform over one clock period. The | ||
+ | first value corresponds to the first rising | ||
+ | transition after time zero. The numbers should | ||
+ | represent one full clock period. If you omit this | ||
+ | option, a default waveform is assumed: the leading | ||
+ | edge occurs at 0 and the trailing edge occurs at | ||
+ | the midpoint of the period, such that a symmetric | ||
+ | clock is generated. | ||
+ | </code> | ||
+ | |||
+ | ====== Post-synthesis simulation ====== | ||
+ | |||
+ | Just simulate the synthesized Verilog netlist with the original testbench ! | ||
+ | |||
+ | You must include detailed references to the Verilog description (source file/compiled Verilog) | ||
+ | of STD cells for the technology you are working with | ||
+ | |||
+ | <code> | ||
+ | irun technology.v synthesized.v tb_design.v | ||
+ | </code> | ||
+ | |||
+ | |||
+ | |||
+ | Complete tutorial: | ||
+ | |||
+ | [[http://www.siue.edu/~gengel/ece484LabMaterial/RTLsynthesisTut.pdf]] | ||
====== ====== | ====== ====== |