Differenze
Queste sono le differenze tra la revisione selezionata e la versione attuale della pagina.
| Entrambe le parti precedenti la revisione Revisione precedente | |||
|
vlsi:workbook:digital:howtos [02/08/2013 13:56] pacher |
vlsi:workbook:digital:howtos [17/01/2014 16:10] (versione attuale) goerres |
||
|---|---|---|---|
| Linea 11: | Linea 11: | ||
| - | ===== How to ... ===== | + | ===== How to prevent synthesizer from merging/removing cells? ===== |
| - | Answer... | + | === Problem description === |
| + | During synthesis, the synthesizer runs several optimization algorithms. These algorythms search in the VHDL/Verilog description for constructs, which can be simplified to save the amount of standard cells used. Sometimes, the designer would like to introduce a certain structure on purpose, for instance redundancy for single event upset (SEU) protection. From the synthesizer's point of view this is useless logic, hence it removes this. | ||
| + | === Solution === | ||
| + | //After// running ''elaborate <designName>'' in your initialization script, you have to set some options //before// the following ''synthesize'' step. | ||
| + | |||
| + | == Prevent merging == | ||
| + | Two, let's say flip flops, doing exactly the same to get some redundancy, will be merged into just one flip flop. Preventing this merge operation is done with: | ||
| + | <code>set_attribute optimize_merge_seq false [find /path/to/instance/ -instance <instance_name>]</code> | ||
| + | |||
| + | As an example a command I used in one of my projects (including * as wildcards): | ||
| + | <code>set_attribute optimize_merge_seq false [find /designs/TDC_CTRL_top/instances_hier/dut_wtacgenerator_*/instances_seq/ -instance state_reg*]</code> | ||
| + | |||
| + | //Hint:// To get the path to your instance, use the terminal from which you started encounter. There you can browse unix-like with ''cd'' and ''ls'' through your design hierachy. | ||
| + | |||
| + | |||
| + | == Prevent cell removal == | ||
| + | Similarly, you might consider a scenario where a certain cell from the library is introduced into the desgin. In my case I needed a delay cell, which of course didn't contribute to the logic. Therefore, the synthesizer wanted to remove this cell again. | ||
| + | |||
| + | At the same position as before, call this command to deactivate removal of library cells: | ||
| + | <code>set_attribute preserve true [find . -libcell DEL1M1NM]</code> | ||
| + | |||
| + | If you want a set of cells preserved, use asteriks as wildcards: | ||
| + | <code>set_attribute preserve true [find . -libcell DEL*]</code> | ||
| + | |||
| + | Check in the encounter window if your changes where successful and you still see the intended cells. | ||
| ===== How to ... ===== | ===== How to ... ===== | ||