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[ __[[vlsi:home|Home]]__ ] | [ __[[vlsi:home|Home]]__ ] | ||
+ | [ __[[vlsi:workbook|Back]]__ ] | ||
[ __[[vlsi:workbook|Design WorkBook]]__ ] | [ __[[vlsi:workbook|Design WorkBook]]__ ] | ||
[ __[[vlsi:workbook:analog#contents|Contents]]__ ] | [ __[[vlsi:workbook:analog#contents|Contents]]__ ] | ||
[ __[[vlsi:workbook:analog:webtutorials|Third party tutorials]]__ ] | [ __[[vlsi:workbook:analog:webtutorials|Third party tutorials]]__ ] | ||
+ | [ __[[vlsi:workbook:analog:youtube|Videos]]__ ] | ||
[ __[[vlsi:resources:books|Books]]__ ] | [ __[[vlsi:resources:books|Books]]__ ] | ||
[ __[[vlsi:workbook:glossary|Glossary]]__ ] | [ __[[vlsi:workbook:glossary|Glossary]]__ ] | ||
[ __[[vlsi:workbook:analog:howtos|HowTo's]]__ ] | [ __[[vlsi:workbook:analog:howtos|HowTo's]]__ ] | ||
[ __[[vlsi:workbook:analog:faqs|FAQs]]__ ] | [ __[[vlsi:workbook:analog:faqs|FAQs]]__ ] | ||
+ | [ __[[vlsi:workbook:analog:kpas|Known problems and solutions]]__ ] | ||
\\ | \\ | ||
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references will be included in the tutorials description. As a matter of fact we mention | references will be included in the tutorials description. As a matter of fact we mention | ||
a few very standard layers (e.g. M1 and M2 metal layers) which are common to all technologies. | a few very standard layers (e.g. M1 and M2 metal layers) which are common to all technologies. | ||
+ | |||
+ | Layout examples with the **[[http://www.layouteditor.net/|LayoutEditor]]** open source software | ||
extract a simple **sandwitch metal-to-metal capacitor**, which is another technology-independent example | extract a simple **sandwitch metal-to-metal capacitor**, which is another technology-independent example | ||
+ | To get started with SPICE you can refere to __[[vlsi:workbook:analog:ltspice|LTspice pages]]__ | ||
A collection of questions abaout analog design with Cadence has been collected in form of | A collection of questions abaout analog design with Cadence has been collected in form of | ||
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* Running Cadence Virtuoso | * Running Cadence Virtuoso | ||
* Quitting the session | * Quitting the session | ||
+ | |||
+ | * **[[vlsi:workbook:analog:infrastructure|Analog design infrastructure]]** | ||
+ | * Introduction | ||
+ | * Technology files, libraries, LEF/DEF etc. | ||
* **[[vlsi:workbook:analog:hierarchy|Design hierarchy]]** | * **[[vlsi:workbook:analog:hierarchy|Design hierarchy]]** | ||
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* Tutorial 6 - ... | * Tutorial 6 - ... | ||
* [[vlsi:analog_schematic_tutorials#third_party_video_tutorials|Third party video tutorials]] | * [[vlsi:analog_schematic_tutorials#third_party_video_tutorials|Third party video tutorials]] | ||
+ | |||
+ | * **[[vlsi:workbook:analog:schemref|Schematic-entry references]]** | ||
+ | * Introduction | ||
+ | * .... | ||
+ | * Iterated instances (vectors) | ||
+ | * ... | ||
+ | * ... | ||
* **[[vlsi:workbook:analog:simref|Simulation references]]** | * **[[vlsi:workbook:analog:simref|Simulation references]]** | ||
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* [[vlsi:analog_advancedsim#monte_carlo_simulations|Monte Carlo simulations]] | * [[vlsi:analog_advancedsim#monte_carlo_simulations|Monte Carlo simulations]] | ||
- | * **[[vlsi:workbook:analog:veriloga|Creating analog behavioral models with Verilog-A]]** | + | |
- | * Introduction | + | * **[[vlsi:workbook:analog:doc|Include documentation in your designs]]** |
- | * Reference documentation | + | * Introduction |
- | * ... | + | * Add notes and comments to schematics |
- | * ... | + | * Creating text cell views |
+ | * Include documentation in ADE XL | ||
+ | * Datasheets generation | ||
+ | * ... | ||
* **[[vlsi:workbook:analog:ocean|Running simulations using OCEAN]]** | * **[[vlsi:workbook:analog:ocean|Running simulations using OCEAN]]** | ||
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* ... | * ... | ||
* ... | * ... | ||
+ | |||
+ | * **[[vlsi:workbook:mixed|Introduction to Mixed-Signal simulation with Cadence tools]]** | ||
+ | * Introduction | ||
+ | * ... | ||
+ | * ... | ||
+ | |||
* **[[vlsi:workbook:analog:layout:intro|Layout (an introduction)]]** | * **[[vlsi:workbook:analog:layout:intro|Layout (an introduction)]]** | ||
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* Differential pair | * Differential pair | ||
* Ring oscillator | * Ring oscillator | ||
- | |||
- | * **[[vlsi:workbook:analog:layout:verification|Physical verification]]** | ||
- | * Introduction | ||
- | * Tools overview | ||
- | * Design rules | ||
- | * Design Rule Check (DRC) | ||
- | * Electrical Rule Check (ERC) | ||
- | * Layout-versus-Schematic (LVS) | ||
- | |||
- | * **[[vlsi:workbook:analog:layout:assura|Assura tutorial]]** | ||
- | * Introduction | ||
- | * Documentation | ||
- | * Environment setup | ||
- | * Assura DRC | ||
- | * Assura LVS | ||
- | * Assura QRC | ||
- | |||
- | * **[[vlsi:workbook:analog:layout:calibre|Calibre tutorial]]** | ||
- | * Introduction | ||
- | * Documentation | ||
- | * Environment setup | ||
- | * Calibre DRC | ||
- | * Calibre LVS | ||
- | * Calibre CRX | ||
* **[[vlsi:workbook:analog:layout:pex|Post-Layout simulations]]** | * **[[vlsi:workbook:analog:layout:pex|Post-Layout simulations]]** | ||
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* Parasitic extraction | * Parasitic extraction | ||
* Simulation of the extracted netlist | * Simulation of the extracted netlist | ||
+ | |||
+ | * **[[vlsi:workbook:analog:layout:tutorials:capacitor|Full example: a parallel-plates capacitor]]** | ||
* **[[vlsi:workbook:analog:howtos|HowTo's]]** | * **[[vlsi:workbook:analog:howtos|HowTo's]]** |