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- | {{ :vlsi:workinprogress.png?100}} | ||
- | ====== Part II - Analog and mixed-mode IC design ====== | ||
- | [ __[[vlsi:home|Home]]__ ] | ||
- | [ __[[vlsi:workbook|Design WorkBook]]__ ] | ||
- | [ __[[vlsi:workbook:analog:main#contents|Contents]]__ ] | ||
- | [ __[[vlsi:resources:webtutorials|Third party tutorials]]__ ] | ||
- | [ __[[vlsi:resources:books|Books]]__ ] | ||
- | [ __[[vlsi:workbook:glossary|Glossary]]__ ] | ||
- | [ __[[vlsi:workbook:analog:howtos|HowTo's]]__ ] | ||
- | [ __[[vlsi:workbook:analog:faqs|FAQs]]__ ] | ||
- | |||
- | \\ | ||
- | The second part of the WorkBook... | ||
- | |||
- | **technology-independent tutorials** | ||
- | vanilla environment setups | ||
- | simple SPICE model files that can be downloaded without restrictions from the Web | ||
- | |||
- | Although layout exercises have been run attached to a specific technology, no technology | ||
- | references will be included in the tutorials description. As a matter of fact we mention | ||
- | a few very standard layers (e.g. M1 and M2 metal layers) which are common to all technologies. | ||
- | |||
- | |||
- | extract a simple **sandwitch metal-to-metal capacitor**, which is another technology-independent example | ||
- | |||
- | |||
- | A collection of questions abaout analog design with Cadence has been collected in form of | ||
- | __[[vlsi:workbook:analog:howtos|HowTo's]]__ and __[[vlsi:workbook:analog:faqs|FAQs]]__. | ||
- | |||
- | |||
- | == Contents == | ||
- | |||
- | * **[[vlsi:analog_start|Getting started]]** | ||
- | * Introduction | ||
- | * Tools overview | ||
- | * Documentation | ||
- | * Setting up the UNIX evironment | ||
- | * Running Cadence Virtuoso | ||
- | * Quitting the session | ||
- | |||
- | * **[[vlsi:workbook:analog:hierarchy|Design hierarchy]]** | ||
- | * Introduction | ||
- | * Libraries | ||
- | * The ''cds.lib'' file | ||
- | * Cells | ||
- | * Cell views | ||
- | * Using the Library Manager | ||
- | * Creating a new library | ||
- | * Creating a new cell | ||
- | * Opening an existing cell | ||
- | * Copying and deleting | ||
- | * Managing libraries with the Library Path Editor | ||
- | |||
- | * **[[vlsi:workbook:analog:cdsenv|Cadence environment and setup files]]** | ||
- | * [[vlsi:workbook:analog:cdsenv#introduction|Introduction]] | ||
- | * [[vlsi:workbook:analog:cdsenv#reference_documentation|Reference documentation]] | ||
- | * [[vlsi:workbook:analog:cdsenv#sample_files|Sample files]] | ||
- | * [[vlsi:workbook:analog:cdsenv#.cadence_directories|.cadence directories]] | ||
- | * [[vlsi:workbook:analog:cdsenv#.cdsenv_and_.cdsinit_initialization_files|.cdsenv and .cdsinit initialization files]] | ||
- | * [[vlsi:workbook:analog:cdsenv#.cdsinit_tech|.cdsinit_tech]] | ||
- | * [[vlsi:workbook:analog:cdsenv#libinit.il|libInit.il]] | ||
- | * [[vlsi:workbook:analog:cdsenv#cds.log|CDS.log]] | ||
- | * [[vlsi:workbook:analog:cdsenv#.simrc|.simrc]] | ||
- | * [[vlsi:workbook:analog:cdsenv#.cdsplotinit|.cdsplotinit]] | ||
- | * [[vlsi:workbook:analog:cdsenv#cds.lib_library_definition_file|cds.lib library definition file]] | ||
- | * [[vlsi:workbook:analog:cdsenv#display.drf|display.drf]] | ||
- | * [[vlsi:workbook:analog:cdsenv#bindkeys|Bindkeys]] | ||
- | * [[vlsi:workbook:analog:cdsenv#some_customization_examples|Some customization examples]] | ||
- | |||
- | * **[[vlsi:analog_schematic_tutorials|Basic analog design tutorials]]** | ||
- | * Introduction | ||
- | * Environment setup | ||
- | * Tutorial 1 - Basic NMOS characteristics | ||
- | * Tutorial 2 - Common-source amplifier | ||
- | * Tutorial 3 - The CMOS inverter | ||
- | * Tutorial 4 - A two stage OPAMP with Miller compensation | ||
- | * Tutorial 5 - ... | ||
- | * Tutorial 6 - ... | ||
- | * [[vlsi:analog_schematic_tutorials#third_party_video_tutorials|Third party video tutorials]] | ||
- | |||
- | * **[[vlsi:analog_simref|Simulation references]]** | ||
- | * [[vlsi:analog_simref#introduction|Introduction]] | ||
- | * [[vlsi:analog_simref#reference_documentation|Reference documentation]] | ||
- | * [[vlsi:analog_simref#dc_operating_points|DC operating points]] | ||
- | * [[vlsi:analog_simref#power_consumption_evaluation|Power consumption evaluation]] | ||
- | * [[vlsi:analog_simref#ADE_simulation_options|ADE simulation options]] | ||
- | * [[vlsi:analog_simref#total_input_output_impedance_simulation|Total input/output impedance simulation]] | ||
- | * [[vlsi:analog_simref#noise_analyses|Noise analyses]] | ||
- | * .... | ||
- | |||
- | * **[[vlsi:analog_techniques|Design techniques]]** | ||
- | * Introduction | ||
- | * MOS small signal model validity | ||
- | * Analog design in very deep submicron technologies | ||
- | * Rules of thumb for transistor sizing | ||
- | * Some standard analog topologies | ||
- | |||
- | * **[[vlsi:analog_bad|Bad analog design practices]]** | ||
- | * Introduction | ||
- | * ... | ||
- | |||
- | * **[[vlsi:analog_advancedsim|Advanced analog design simulations]]** | ||
- | * Introduction | ||
- | * Getting started with ADE XL | ||
- | * Reference documentation | ||
- | * Corner analysis | ||
- | * [[vlsi:analog_advancedsim#monte_carlo_simulations|Monte Carlo simulations]] | ||
- | |||
- | * **[[vlsi:workbook:analog:veriloga|Creating analog behavioral models with Verilog-A]]** | ||
- | * Introduction | ||
- | |||
- | * **[[vlsi:workbook:analog:ocean|Running simulations using OCEAN]]** | ||
- | * Introduction | ||
- | * ... | ||
- | * ... | ||
- | |||
- | * **[[vlsi:analog_layout_intro|Layout (an introduction)]]** | ||
- | * Introduction | ||
- | * Tools overview | ||
- | * Reference documentation | ||
- | * Environment setup | ||
- | * Load standard bindkeys | ||
- | * Starting Cadence Virtuoso Layout Editor L/XL | ||
- | * Setting user preferences | ||
- | * The Layer Palette | ||
- | |||
- | * **[[vlsi:analog_layout_tutorials|Basic layout tutorials]]** | ||
- | * Introduction | ||
- | * Create a ruler | ||
- | * Draw a simple metal layer | ||
- | * Edit objects | ||
- | * Merge layers | ||
- | * View the layer stack | ||
- | * Create a text label | ||
- | * Create a pin | ||
- | |||
- | * **[[vlsi:analog_layout_pcells|Working with parametrized cells]]** | ||
- | * Introduction | ||
- | * Substrate contacts | ||
- | * NMOS layout | ||
- | * PMOS layout | ||
- | |||
- | * **[[vlsi:analog_layout_techniques|Layout techniques]]** | ||
- | * Introduction | ||
- | * Multi-finger transistors | ||
- | * Common centroid layout | ||
- | * Latch-up | ||
- | |||
- | * **[[vlsi:analog_layout_examples|Standard layout examples]]** | ||
- | * Inverter layout | ||
- | * Common source amplifier | ||
- | * NAND gate | ||
- | * NOR gate | ||
- | * Differential pair | ||
- | * Ring oscillator | ||
- | |||
- | * **[[vlsi:analog_layout_verification|Physical verification]]** | ||
- | * Introduction | ||
- | * Tools overview | ||
- | * Design rules | ||
- | * Design Rule Check (DRC) | ||
- | * Electrical Rule Check (ERC) | ||
- | * Layout-versus-Schematic (LVS) | ||
- | |||
- | * **[[vlsi:analog_layout_assura|Assura tutorial]]** | ||
- | * Introduction | ||
- | * Documentation | ||
- | * Environment setup | ||
- | * Assura DRC | ||
- | * Assura LVS | ||
- | * Assura QRC | ||
- | |||
- | * **[[vlsi:analog_layout_calibre|Calibre tutorial]]** | ||
- | * Introduction | ||
- | * Documentation | ||
- | * Environment setup | ||
- | * Calibre DRC | ||
- | * Calibre LVS | ||
- | * Calibre CRX | ||
- | |||
- | * **[[vlsi:analog_layout_postsim|Post-Layout simulations]]** | ||
- | * Introduction | ||
- | * Parasitic extraction | ||
- | * Simulation of the extracted netlist | ||
- | |||
- | * **[[vlsi:workbook:analog:howtos|HowTo's]]** | ||
- | |||
- | * **[[vlsi:workbook:analog:faqs|FAQs]]** | ||
- | |||
- | |||
- | |||
- | **Keywords:** | ||
- | |||
- | ====== ====== | ||
- | \\ | ||
- | ---- | ||
- | \\ | ||
- | Maintainers: [[lattuca@NOSPAMto.infn.it|Alessandra Lattuca]], [[pacher@NOSPAMto.infn.it|Luca Pacher]]\\ | ||
- | Last update: [[pacher@NOSPAMto.infn.it|Luca Pacher]] - Arp 10, 2013 |