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vlsi:workbook:analog:hierarchy [02/08/2013 13:51]
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-====== Design hierarchy ======+====== Design hierarchy ​in Cadence IC (Virtuoso) ​======
  
 [ __[[vlsi:​home|Home]]__ ] [ __[[vlsi:​home|Home]]__ ]
-[ __[[vlsi:​workbook|VLSI Design WorkBook]]__ ] +[ __[[vlsi:​workbook|Design WorkBook]]__ ] 
-[ __[[vlsi:analog_main#​contents|Back to index]]__ ]+[ __[[vlsi:workbook:​analog#​contents|Back to index]]__ ]
  
  
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       * Opening an existing cell       * Opening an existing cell
       * Copying and deleting       * Copying and deleting
-      * Managing libraries with the Library Path Editor ​+      * Managing libraries with the Library Path Editor 
 +      * Cadence default libraries
  
 **Keywords:​** **Keywords:​**
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 Cosa fondamentale,​ dal punto di vista UNIX sono **UNIX directories** Cosa fondamentale,​ dal punto di vista UNIX sono **UNIX directories**
 +
 +
 +===== Organizing libraries with categories =====
 +
 +[[http://​www.ece.rice.edu/​~cavallar/​cadence/​tutorial/​library.html]]
 +
 +
 +**File -> New -> Category ...**
 +
 +Show categories
 +
  
 ===== Cell views ===== ===== Cell views =====
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 advanced simulations such as **corner analysis** and **Monte Carlo simulations** ​ advanced simulations such as **corner analysis** and **Monte Carlo simulations** ​
 in **Virtuoso ADE XL** e gli stati sono salvati in a particular cell view of the type //adexl// in **Virtuoso ADE XL** e gli stati sono salvati in a particular cell view of the type //adexl//
 +
 +
 +**text**\\
 +posso includere file plain text per la documentazione direttamente nella cella!
 +
 +File => New => Cell View e poi scelgo come Type **text**
 +
  
  
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 +Important! **attach vs. referencing** !!!
 +
 +attach = **static** technology database
 +
 +reference = **incremental technology database (ITDB)** ​
 +
 +For example, if you have to add a custom via or routing constraint ​
 +you must modify this main PDK which may cause problems for other users.
 +An ITDB is more flexible because updates can be made directly to the ITDB without effecting the base PDK. 
 +You can also define multiple ITDBs which reference the same base PDK.
  
 ===== Creating a new cell ===== ===== Creating a new cell =====
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 Solo per dire che il ''​cds.lib''​ file lo posso editare anche via GUI Solo per dire che il ''​cds.lib''​ file lo posso editare anche via GUI
 +
 +
 +
 +
 +====== Cadence IC default libraries ======
 +
 +
 +Defined in the default ''​cds.lib''​ file
 +
 +''​$IC_DIR/​tools/​dfII/​local/​cds.lib''​
 +
 +
 +
 +<​code>​
 +DEFINE analogLib ​       $IC_DIR/​tools/​dfII/​etc/​cdslib/​artist/​analogLib
 +DEFINE functional $IC_DIR/​tools/​dfII/​etc/​cdslib/​artist/​functional
 +DEFINE sbaLib ​          ​$IC_DIR/​tools/​dfII/​etc/​cdslib/​artist/​sbaLib
 +DEFINE basic            $IC_DIR/​tools/​dfII/​etc/​cdslib/​basic
 +DEFINE US_8ths ​         $IC_DIR/​tools/​dfII/​etc/​cdslib/​sheets/​US_8ths
 +--
 +DEFINE aExamples ​       $IC_DIR/​tools/​dfII/​samples/​artist/​aExamples
 +DEFINE ahdlLib ​         $IC_DIR/​tools/​dfII/​samples/​artist/​ahdlLib
 +DEFINE bmslib ​          ​$IC_DIR/​tools/​dfII/​samples/​artist/​bmslib
 +DEFINE passiveLib $IC_DIR/​tools/​dfII/​samples/​artist/​passiveLib
 +DEFINE pllLib ​          ​$IC_DIR/​tools/​dfII/​samples/​artist/​pllLib
 +DEFINE pllMMLib ​        ​$IC_DIR/​tools/​dfII/​samples/​artist/​pllMMLib
 +DEFINE rfExamples $IC_DIR/​tools/​dfII/​samples/​artist/​rfExamples
 +DEFINE rfLib            $IC_DIR/​tools/​dfII/​samples/​artist/​rfLib
 +DEFINE solutions ​       $IC_DIR/​tools/​dfII/​samples/​artist/​solutions
 +DEFINE training ​        ​$IC_DIR/​tools/​dfII/​samples/​artist/​training
 +--
 +DEFINE ieLib            $IC_DIR/​tools/​dfII/​samples/​artist/​mixSig/​ieModels/​ieLib
 +DEFINE ieTest ​          ​$IC_DIR/​tools/​dfII/​samples/​artist/​mixSig/​ieTest/​ieTestLib
 +--
 +DEFINE sample ​          ​$IC_DIR/​tools/​dfII/​samples/​cdslib/​sample
 +DEFINE ISO_2_5mm ​       $IC_DIR/​tools/​dfII/​samples/​cdslib/​sheets/​ISO_2_5mm
 +DEFINE ISO_2mm ​         $IC_DIR/​tools/​dfII/​samples/​cdslib/​sheets/​ISO_2mm
 +DEFINE US_10ths ​        ​$IC_DIR/​tools/​dfII/​samples/​cdslib/​sheets/​US_10ths
 +DEFINE US_16ths ​        ​$IC_DIR/​tools/​dfII/​samples/​cdslib/​sheets/​US_16ths
 +
 +DEFINE substrateLib ​    ​$IC_DIR/​share/​sna/​etc/​cdslib/​substrateLib
 +
 +DEFINE connectLib ​       $INCISIVE_DIR/​tools/​affirma_ams/​etc/​connect_lib/​connectLib
 +--
 +-- DEFINE std $IC_DIR/​tools/​leapfrog/​files/​STD
 +-- DEFINE ieee $IC_DIR/​tools/​leapfrog/​files/​IEEE
 +-- DEFINE synergy $IC_DIR/​tools/​leapfrog/​files/​SYNERGY
 +-- DEFINE xl $IC_DIR/​tools/​leapfrog/​files/​XL
 +-- DEFINE valid $IC_DIR/​tools/​leapfrog/​files/​VALID
 +-- DEFINE sim $IC_DIR/​tools/​leapfrog/​files/​SIM
 +</​code>​
 +
 +
 +Don't clutter your Library Manager with unused libraries!!! Include only necessary libraries indeed!