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--- vlsi:workbook:analog:hierarchy [20/08/2013 23:17]
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+++ vlsi:workbook:analog:hierarchy [18/08/2014 14:05]
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-====== Design hierarchy ======
+====== Design hierarchy in Cadence IC (Virtuoso) ======
 [ __[[vlsi:home|Home]]__ ]
-[ __[[vlsi:workbook|VLSI Design WorkBook]]__ ]
+[ __[[vlsi:workbook|Design WorkBook]]__ ]
-[ __[[vlsi:workbook:analog:main#contents|Back to index]]__ ]
+[ __[[vlsi:workbook:analog#contents|Back to index]]__ ]
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       * Opening an existing cell
       * Copying and deleting
       * Managing libraries with the Library Path Editor
+      * Cadence default libraries
 **Keywords:**
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 Cosa fondamentale, dal punto di vista UNIX sono **UNIX directories**
+===== Organizing libraries with categories =====
+[[http://www.ece.rice.edu/~cavallar/cadence/tutorial/library.html]]
+**File -> New -> Category ...**
+Show categories
 ===== Cell views =====
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 advanced simulations such as **corner analysis** and **Monte Carlo simulations**
 in **Virtuoso ADE XL** e gli stati sono salvati in a particular cell view of the type //adexl//
+**text**\\
+posso includere file plain text per la documentazione direttamente nella cella!
+File => New => Cell View e poi scelgo come Type **text**
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+Important! **attach vs. referencing** !!!
+attach = **static** technology database
+reference = **incremental technology database (ITDB)**
+For example, if you have to add a custom via or routing constraint
+you must modify this main PDK which may cause problems for other users.
+An ITDB is more flexible because updates can be made directly to the ITDB without effecting the base PDK.
+You can also define multiple ITDBs which reference the same base PDK.
 ===== Creating a new cell =====