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vlsi:resources:systemverilog [02/07/2015 22:49] pacher |
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[ __[[vlsi:workbook|Design WorkBook]]__ ] | [ __[[vlsi:workbook|Design WorkBook]]__ ] | ||
[ __[[vlsi:resources:books|Books]]__ ] | [ __[[vlsi:resources:books|Books]]__ ] | ||
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+ | //IEEE std 1800-2012// \\ | ||
+ | [[http://www.eda.org/sv/SystemVerilog_3.1a.pdf|SystemVerilog 3.1a Language Reference Manual]] | ||
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+ | //OVM/UVM User's Guide// | ||
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+ | \\ | ||
+ | ====== Syntax highlighting for the Gedit text editor ====== | ||
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+ | **1.** make a copy of the Verilog language style | ||
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+ | ''/usr/share/gtksourceview-2.0/language-specs/verilog.lang'' | ||
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+ | **2.** modify the language id as | ||
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+ | <code> | ||
+ | <language id="systemverilog" _name="SystemVerilog" version="2.0" _section="Sources"> | ||
+ | </code> | ||
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+ | and | ||
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+ | <code> | ||
+ | <context id="systemverilog"> <!-- modified from verilog to systemverilog --> | ||
+ | <include> | ||
+ | <context ref="line-comment"/> | ||
+ | <context ref="block-comment"/> | ||
+ | <context ref="close-comment-outside-comment"/> | ||
+ | <context ref="compiler-directive"/> | ||
+ | <context ref="keywords"/> | ||
+ | <context ref="gates"/> | ||
+ | <context ref="types"/> | ||
+ | <context ref="binary-number"/> | ||
+ | <context ref="octal-number"/> | ||
+ | <context ref="decimal-number"/> | ||
+ | <context ref="hexadecimal-number"/> | ||
+ | </include> | ||
+ | </context> | ||
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+ | </code> | ||
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+ | **3.** change the default file extension | ||
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+ | <code> | ||
+ | <property name="globs">*.sv</property> | ||
+ | </code> | ||
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+ | **4.** add new SystemVerilog reserved words by following the XML syntax | ||
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+ | <code> | ||
+ | <keyword>word</keyword> | ||
+ | </code> | ||
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