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Tutorial: ADC a 8 bit

Nella cartella di lavoro creare:

• Il file hdl.var

define WORK worklib
include $CDS_INST_DIR/tools/inca/files/hdl.var

• Il file cds.lib

define worklib /users/panati/projects/ALICE/ITS/syn_tj/netlist_in/worklib
include $CDS_INST_DIR/tools/inca/files/cds.lib

• Un file di codice Verilog-AMS con estensione adc.vams

`include "disciplines.vams"
`timescale 1ns / 1ps

	module adc (out, in, clk);
		parameter integer bits = 8 from [1:24];

	// resolution (bits)
		parameter real fullscale = 1.0;

	// input range is from 0 to fullscale (V)
		parameter real td = 0;

	// delay from clock to output (ns)
		input in, clk;
		output out;
		voltage in;
		reg [0:bits-1] out;
		reg over;
		real sample, midpoint;
		integer i;

	always @(posedge clk) begin
		sample = V(in);
		midpoint = fullscale/2.0;
		for (i = bits - 1; i >= 0; i = i - 1) begin
			over = (sample > midpoint);
			if (over)
			sample = sample - midpoint;
			sample = 2.0*sample;
			out[i] <= #(td) over;
		end
		end
	endmodule

• Un file di test bench Verilog-AMS con estensione tb_adc.vams

`timescale 10ns / 10ps
`include "disciplines.vams"
	module testbench ();
		electrical gnd;
		ground gnd;
		reg clk;
		wire [0:7] out;
		integer ii;
		reg [0:7] plot_out;
		initial clk=0;
		always #1 clk=~clk;
		always @(out) for (ii=0; ii<8; ii=ii+1) plot_out[ii] <= out[7-ii];
		adc adc0 (out, in, clk);
		vsource #(.type("sine"), .ampl(0.5), .dc(0.5), .freq(1M)) v0 (in, gnd);
	endmodule

• Un file di Connect Rules con estensione connectrules.vams

`include "disciplines.vams"
	connectrules my_connectrules;
	connect electrical, voltage resolveto electrical;
	endconnectrules

• Un file di controllo per la simulazione con estensione run.scs

*
transient tran stop=100us

• Un file di run con estensione run.tcl

database -open waves -into waves.shm -default
probe -create testbench -depth all -shm -waveform
run 100us
exit

Come funzionano questi files?

Per il linguaggio Verilog-AMS vedi i seguenti links:

• http://www.eda.org/verilog-ams/htmlpages/tc-docs/lrm/2.0/
• http://en.wikipedia.org/wiki/Verilog-AMS
• http://www.designers-guide.org/VerilogAMS/
• http://www.accellera.org/activities/committees/verilog-ams/
• http://www.eda.org/twiki/bin/view.cgi/VerilogAMS
• http://www.eda.org/verilog-ams/htmlpages/examples.html
• http://www.cadence.com/Community/forums/p/27170/1326638.aspx
• http://www.edaboard.com/thread302202.html

Per il linguaggio Verilog-A vedi i seguenti links:

• http://www.silvaco.com/products/analog_mixed_signal/behavioral_modeling/verilog_A.html
• http://venividiwiki.ee.virginia.edu/mediawiki/index.php/ICDesignVerilogA
• http://www.asic-world.com/verilog/
• http://cp.literature.agilent.com/litweb/pdf/genesys200801/sim/amk/verilog-a_tutorial.htm
• http://asic.co.in/Index_files/tutorials/verilog_a_tutorial_p1.htm

Per il linguaggio Verilog-D vedi i seguenti links:

• http://bawankule.com/verilogfaq/page2.html
• http://www.asic-world.com/verilog/

Per il linguaggio VHDL-AMS vedi i seguenti links:

• http://www.theoinf.tu-ilmenau.de/~twangl/VHDL-AMS_online_en/Home.html
• Quick ref
• Introduction To The VHDL-AMD Modeling Language
• Introduction a le VHDL-AMS (FR)

Aprire NCLaunch e abilitare nella casella “Filters” le estensioni .vams digitando *.vams:

IMMAGINE 01

Nella Console Window digitare:

nclaunch>  ncvlog -ams -work worklib connectrules.vams

nclaunch>  ncvlog -ams adc.vams

nclaunch>  ncvlog -ams tb_adc.vams

nclaunch>  ncelab testbench my_connectrules -timescale 10ps/1ps

nclaunch>  ncsim -GUI testbench -messages -analogcontrol run.scs -input run.tcl

IMMAGINE 02

Si aprono le seguenti finestre:

IMMAGINE 03

IMMAGINE 04

IMMAGINE 05

IMMAGINE 06

IMMAGINE 07

… Done!

LINK ALLE IMMAGINI: http://ge.tt/9ej58zD1