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Queste sono le differenze tra la revisione selezionata e la versione attuale della pagina.

--- vlsi:personalpages:pacher [06/05/2015 11:33]
pacher
+++ vlsi:personalpages:pacher [07/01/2019 09:15] (versione attuale)
pacher [Luca Pacher - Wiki personal page]
@@ Linea 8: / Linea 8: @@
 [ __[[vlsi:personalpages:pacher:cmstk|CMS tracker]]__ ]
 [ __[[vlsi:projects:chipix65|CHIPIX65]]__ ]
-[ __[[vlsi:personalpages:pacher#notes|Notes]]__ ]
+[ __[[vlsi:personalpages:pacher:notes|Notes]]__ ]
 [ __[[vlsi:personalpages:pacher:linux|Linux stuffs]]__ ]
 [ __[[vlsi:personalpages:pacher:linux:sl6x|SL 6.x]]__ ]
@@ Linea 14: / Linea 14: @@
 [ __[[vlsi:personalpages:pacher:literature|Useful references]]__ ]
 [ __[[vlsi:personalpages:pacher:history|History]]__ ]
-[ __[[vlsi:personalpages:pacher:didattica|Teaching assistance]]__ ]
+[ __[[vlsi:personalpages:pacher:didattica|Teaching]]__ ]
+[ __[[vlsi:personalpages:pacher:fpga|FPGA]]__ ]
 [ __[[vlsi:workbook2:skill|SKILL]]__ ]
 [ __[[vlsi:personalpages:pacher:freepdk|FreePDK/GPDK]]__ ]
 [ __[[vlsi:personalpages:pacher:digital|Digital IC design]]__ ]
 [ __[[vlsi:personalpages:pacher:test|Test]]__ ]
+[ __[[vlsi:personalpages:pacher:devel|/devel]]__ ]
 [ __[[vlsi:personalpages:pacher:tmp|/tmp]]__ ]
 [ __[[vlsi:private:personalpages:pacher:agenda|Agenda]]__ ]
 [ __[[vlsi:personalpages:pacher:notes|Notes]]__ ]
 [ __[[vlsi:personalpages:pacher:vepix53|VEPIX53 (tmp)]]__ ]
+[ __[[vlsi:personalpages:pacher:phy100|Phy100]]__ ]
+[ __[[vlsi:personalpages:pacher:asn|ASN]]__ ]
+[ __[[vlsi:personalpages:pacher:lnxmix|CERN MIC cluster]]__ ]
 \\
 //Don’t forget to have fun. Life is too short.//
 ====== Coordinates ======
-[[http://www.youtube.com/watch?v=j5-yKhDd64s|{{:vlsi:personalpages:pacher:pacher.png?140}}]]
+{{:vlsi:personalpages:pacher:pacher.png?140}}
 \\
-**Turin Office:**       New building - 2nd floor, room B25                  \\
+**Turin Office:**       New building - 2nd floor, room B15                                   \\
-**Phone:**              +39.011.670.7293                               \\
+**Phone:**              +39.011.670.7434                                                     \\
 **E-mail:**             [[luca.pacher@NOSPAMto.infn.it]] | [[luca.pacher@NOSPAMunito.it]]    \\
+**Skype:**              pacher_luca
-**CERN Office:**        13-2-017                                            \\
+**CERN Office:**        13-2-017                                                             \\
-**Phone:**              +41.22.76.72059                                     \\
+**Phone:**              +41.22.76.72059                                                      \\
-**E-mail:**             [[Luca.Pacher@NOSPAMcern.ch]]                  \\
+**E-mail:**             [[Luca.Pacher@NOSPAMcern.ch]]                                        \\
 **MailBox:**            F22910
@@ Linea 47: / Linea 53: @@
 ====== Current position and memberships ======
    * //Not a beginner, not yet a pro... (aiming to become a Cylon)//
-   * Postdoctoral researcher, University of Turin
    * associated to INFN, Section of Turin
    * member of the <nowiki>CMS</nowiki> experiment at CERN
@@ Linea 57: / Linea 62: @@
 ====== About me ======
-**2015 - **  \\
-Postdoctoral research grant, University of Turin, Italy
 \\
-**2011 - 2014**  \\
+**2011 - 2015**  \\
-Ph.D. in Physics and Astrophysics, XXVII cycle, University of Turin, Italy \\
+Ph.D. student in Physics and Astrophysics, XXVII cycle, University of Turin, Italy \\
 Thesis: //Development of Integrated Pixel Front-End Electronics in 65nm CMOS Technology for Extreme Rate and Radiation at HL-LHC//
@@ Linea 88: / Linea 91: @@
    * analog and mixed-signal full-custom IC design (Cadence IC6.1.x environment, Spectre/HSpice)
-   * HDL languages (VHDL, Verilog)
+   * HDL languages (VHDL, Verilog/SystemVerilog)
    * digital IC design (Cadence Incisive, RTL Compiler, Encounter Digital Implementation)
    * physical verification (Cadence Assura and PVS, Mentor Calibre)
@@ Linea 104: / Linea 107: @@
    * silicon detectors, tracking systems
-====== Publications ======
+===== Publications ======
 //A Low-Power Low-Noise Synchronous Pixel Front-End Chain in 65 nm CMOS Technology with Local Fast ToT Encoding
-and Autozeroing for Extreme Rate and Radiation at HL-LHC//, IEEE NSS/MIC 2015, San Diego, CA, US \\ [{{:vlsi:personalpages:pacher:documents:pacher_ieee_nss_2015_abstract_and_summary.pdf|Abstract and summary}}]
+and Autozeroing for Extreme Rate and Radiation at HL-LHC// [{{:vlsi:personalpages:pacher:documents:pacher_ieee_nss_2015_abstract_and_summary.pdf|Abstract and summary}}] \\
+IEEE NSS/MIC 2015, San Diego, CA, US \\
+//Design of a 10-bit segmented current-steering Digital-to-Analog Converter in CMOS 65nm technology for the bias of new generation readout chips in high radiation environment// \\
+[[https://indico.cern.ch/event/357738/session/10/contribution/18]]  \\
+TWEPP 2015, Lisbon
+//Pixel front-end with synchronous discriminator and fast charge measurement for the upgrades of HL-LHC experiments//  \\
+[[https://indico.cern.ch/event/357738/session/10/contribution/153]] \\
+TWEPP 2015, Lisbon
@@ Linea 222: / Linea 238: @@
 ----
-Last update: Dec 23, 2014
+Last update: Jun 23, 2015
 ~~NOTOC~~