Luca Pacher - Wiki personal page

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Don’t forget to have fun. Life is too short.


Turin Office: New building - 2nd floor, room B15
Phone: +39.011.670.7434
E-mail: |
Skype: pacher_luca

CERN Office: 13-2-017
Phone: +
MailBox: F22910

Academic CV [PDF]

Current position and memberships

  • Not a beginner, not yet a pro… (aiming to become a Cylon)
  • associated to INFN, Section of Turin
  • member of the CMS experiment at CERN
  • member of the CERN/RD53 collaboration
  • member of the Italian CHIPIX65 INFN/CSN5 collaboration

About me

2011 - 2015
Ph.D. student in Physics and Astrophysics, XXVII cycle, University of Turin, Italy
Thesis: Development of Integrated Pixel Front-End Electronics in 65nm CMOS Technology for Extreme Rate and Radiation at HL-LHC

Postgraduate degree in Physics (2 years, Master of Science), University of Turin, Italy
Specialization in experimental Nuclear and Particle Physics
Thesis: LePix: Monolithic Pixel Detector for LHC Tracking Systems
Final grade: 110/110 magna cum laude

Undergraduate degree in Physics (3 years, Bachelor of Science), University of Turin, Italy
Thesis: Study and Characterization of a Solid State Photodetecor Based on APD
Final grade: 110/110 magna cum laude

Scientific Diploma, Liceo Scientifico Aldo Moro, Rivarolo Canavese (TO), Italy
Final grade: 100/100

Skills and interests

  • analog and mixed-signal full-custom IC design (Cadence IC6.1.x environment, Spectre/HSpice)
  • HDL languages (VHDL, Verilog/SystemVerilog)
  • digital IC design (Cadence Incisive, RTL Compiler, Encounter Digital Implementation)
  • physical verification (Cadence Assura and PVS, Mentor Calibre)
  • system administration (RAID/LVM, X System, TCP/IP, OpenSSH, NFS, CVS/SVN, rsync)
  • CAE tools installation and maintenance
  • FLEXlm-based licensing
  • design kit installation and maintenance
  • Web design (HTML, TWiki/DokuWiki)
  • software programming (C/C++, Python, ROOT/PyROOT)
  • scripting (csh/bash, batch, TCL, SKILL/OCEAN)
  • FPGA programming (Xilinx ISE)
  • test engineering
  • technical writing
  • particle physics
  • silicon detectors, tracking systems

A Low-Power Low-Noise Synchronous Pixel Front-End Chain in 65 nm CMOS Technology with Local Fast ToT Encoding and Autozeroing for Extreme Rate and Radiation at HL-LHC [Abstract and summary]
IEEE NSS/MIC 2015, San Diego, CA, US

Design of a 10-bit segmented current-steering Digital-to-Analog Converter in CMOS 65nm technology for the bias of new generation readout chips in high radiation environment
TWEPP 2015, Lisbon

Pixel front-end with synchronous discriminator and fast charge measurement for the upgrades of HL-LHC experiments
TWEPP 2015, Lisbon

Radiation Tolerance of a Moderate Resistivity Substrate in a Modern CMOS Process (2013)
NIM A 718 347-349

RD Collaboration Proposal: Development of Pixel Readout Integrated Circuits for Extreme Rate and Radiation (2013)

CMS Technical Design Report for the Pixel Detector Upgrade (2012)

Authorship within the CMS Collaboration since Oct 2013, see Inspire

Conferences and workshops

International schools and training Workshops

Phd stuffs

Teaching assistance (TA)

See also Didattica .


  • 6 ore (lezione frontale + esercitazioni con simulatore circuitale LTSpice), Esperimentazioni II (M. Chiosso)


  • 30 ore (lezione frontale + laboratorio, esperienza LePix), Laboratorio Fisica Nucleare e Subnucleare II (M. Costa)
  • 5 ore (esercitazioni con simulatore circuitale PSpice), Elettronica (E. Menichetti)
  • 4 ore (lezione frontale + esercitazioni con simulatore circuitale PSpice), Esperimentazioni II (M. Chiosso)


  • 6 ore (esercitazioni con simulatore circuitale PSpice), Microelettronica (A. Rivetti)

Last update: Jun 23, 2015

  • vlsi/personalpages/pacher.txt
  • Ultima modifica: 07/01/2019 09:15
  • da pacher