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Part II - Analog and mixed-mode IC design
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The second part of the WorkBook…
technology-independent tutorials vanilla environment setups simple SPICE model files that can be downloaded without restrictions from the Web
Although layout exercises have been run attached to a specific technology, no technology references will be included in the tutorials description. As a matter of fact we mention a few very standard layers (e.g. M1 and M2 metal layers) which are common to all technologies.
extract a simple sandwitch metal-to-metal capacitor, which is another technology-independent example
Contents
-
- Introduction
- Tools overview
- Reference documentation
- Setting up the UNIX evironment
- Running Cadence Virtuoso
- Quitting the session
-
- Introduction
- Libraries
- The
cds.lib
file - Cells
- Cell views
- Using the Library Manager
- Creating a new library
- Creating a new cell
- Opening an existing cell
- Copying and deleting
- Managing libraries with the Library Path Editor
-
- Introduction
- Reference documentation
.cadence
directoriescds.lib
library definition file.cdsinit
and.cdsenv
initialization files.cdsinit_tech
libInit.il
.simrc
.plotinit
display.drf
- Customization examples
-
- Introduction
- Tutorial 1 - Basic NMOS characteristics
- Tutorial 2 - Common-source amplifier
- Tutorial 3 - The CMOS inverter
- Tutorial 4 - A two stage OPAMP with Miller compensation
- Tutorial 5 - …
- Tutorial 6 - …
-
- Introduction
- Analyses overview
-
- Introduction
- MOS small signal model validity
- Analog design in very deep submicron technologies
- Rules of thumb for transistor sizing
- Some standard analog topologies
-
- Introduction
- …
-
- Introduction
- Getting started with ADE XL
- Reference documentation
- Corner analysis
- Monte Carlo simulations
-
- Introduction
-
- Introduction
-
- Introduction
- Tools overview
- Reference documentation
- Environment setup
- Load standard bindkeys
- Starting Cadence Virtuoso Layout Editor L/XL
- Setting user preferences
- The Layer Palette
-
- Introduction
- Create a ruler
- Draw a simple metal layer
- Edit objects
- Merge layers
- View the layer stack
- Create a text label
- Create a pin
-
- Introduction
- Substrate contacts
- NMOS layout
- PMOS layout
-
- Introduction
- Multi-finger transistors
- Common centroid layout
- Latch-up
-
- Inverter layout
- Common source amplifier
- NAND gate
- NOR gate
- Differential pair
- Ring oscillator
-
- Introduction
- Tools overview
- Design rules
- Design Rule Check (DRC)
- Electrical Rule Check (ERC)
- Layout-versus-Schematic (LVS)
-
- Introduction
- Documentation
- Environment setup
- Assura DRC
- Assura LVS
- Assura QRC
-
- Introduction
- Documentation
- Environment setup
- Calibre DRC
- Calibre LVS
- Calibre CRX
-
- Introduction
- Parasitic extraction
- Simulation of the extracted netlist
-
- Introduction
Keywords:
Last update: Luca Pacher - Mar 22, 2013