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year Activity

1

1. Study and comparison of TDC architectures via simulations i.e. analogue approach based on Time to Amplitude Converter (TAC) vs digital approach based on Phase Locked Loops (PLL) or
2. Delay Locked Loops (DLL)
3. Selection of the technology best suited for the design
4. Exploring the use of strained lattice hetero-junction bi-polar devices (SiGe)

2

1. q1-q2 Design of critical building blocks of the architecture(s) under analysis in the selected technology. Submission of the blocks.
   
2. q3 Test board design and test set-up preparation
   
3. q4 Test of the building blocks

3

1. q1 Completion of the tests and selection of the architecture
   
2. q1-q2 Design of the first prototype for the selected architecture
   
3. q3 Test board design and test set-up preparation
   
4. q4 Electrical tests of the prototype

4

1. q1-2 Tests of the prototype coped with the detector
   
2. q3-4 Design of the chip demonstrator
   

5

1. q1 Design of the chip demonstrator
   
2. q2 Test board design and test set-up preparation
   
3. q3-q4 Test of the chip demonstrator