Differenze
Queste sono le differenze tra la revisione selezionata e la versione attuale della pagina.
Entrambe le parti precedenti la revisione Revisione precedente Prossima revisione | Revisione precedente Ultima revisione Entrambe le parti successive la revisione | ||
vlsi:workbook:mixed [06/04/2014 23:47] pacher |
vlsi:workbook:mixed [15/07/2014 21:15] pacher |
||
---|---|---|---|
Linea 28: | Linea 28: | ||
[[http://en.wikipedia.org/wiki/Mixed-signal_integrated_circuit]] | [[http://en.wikipedia.org/wiki/Mixed-signal_integrated_circuit]] | ||
+ | [[http://www.cems.uvm.edu/~txia/cadence.htm]] | ||
[[http://jcatsc.com/pages/courses/ee536a.php]] | [[http://jcatsc.com/pages/courses/ee536a.php]] | ||
Linea 44: | Linea 45: | ||
* //[[http://www.europractice.stfc.ac.uk/training/|Introduction to Analogue and Mixed Signal IC Design]]// | * //[[http://www.europractice.stfc.ac.uk/training/|Introduction to Analogue and Mixed Signal IC Design]]// | ||
* //[[http://www.msc.stfc.ac.uk/msc/Training_Courses/|Mixed Signal IC Design and Implementation]]// | * //[[http://www.msc.stfc.ac.uk/msc/Training_Courses/|Mixed Signal IC Design and Implementation]]// | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | |||
+ | Design infrastructure: Verilog-A HDL, AMS simulator, config view, INCISIVE package | ||
+ | |||
+ | |||
+ | ====== Creating analog behavioral models with Verilog-A ====== | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | ===== Reference documentation ===== | ||
+ | |||
+ | ===== Tutorials ===== | ||
+ | |||
+ | un tutorial [[ http://asic.co.in/Index_files/tutorials/verilog_a_tutorial_p1.htm | here ]] | ||
+ | |||
+ | un altro [[ http://www.ee.siue.edu/~jwade/tutorial/cadence_mixed-signal/ams_tutorial.html | here ]] | ||
+ | |||
+ | |||
+ | |||
====== ====== | ====== ====== |