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Mixed-signal = design entry and circuit simulation with a mixture of schematic/SPICE description | Mixed-signal = design entry and circuit simulation with a mixture of schematic/SPICE description | ||
and HDL description | and HDL description | ||
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+ | [[http://en.wikipedia.org/wiki/Mixed-signal_integrated_circuit]] | ||
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+ | [[http://www.cems.uvm.edu/~txia/cadence.htm]] | ||
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+ | [[http://jcatsc.com/pages/courses/ee536a.php]] | ||
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+ | [[http://www2.ece.ohio-state.edu/~bibyk/ece822/MSDK_July_2003.pdf]] \\ | ||
+ | [[http://www2.ece.ohio-state.edu/~bibyk/ee720/ee720.htm]] \\ | ||
+ | [[http://www2.ece.ohio-state.edu/~bibyk/ece822/ece822.htm]] | ||
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+ | Typical examples: Phase Locked Loop circuits (PLLs), A/D and D/A converters | ||
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+ | EUROPRACTICE training references: | ||
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+ | * //[[http://www.europractice.stfc.ac.uk/training/|Introduction to Analogue and Mixed Signal IC Design]]// | ||
+ | * //[[http://www.msc.stfc.ac.uk/msc/Training_Courses/|Mixed Signal IC Design and Implementation]]// | ||
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+ | Design infrastructure: Verilog-A HDL, AMS simulator, config view, INCISIVE package | ||
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+ | ====== Creating analog behavioral models with Verilog-A ====== | ||
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+ | ===== Reference documentation ===== | ||
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+ | ===== Tutorials ===== | ||
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+ | un tutorial [[ http://asic.co.in/Index_files/tutorials/verilog_a_tutorial_p1.htm | here ]] | ||
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+ | un altro [[ http://www.ee.siue.edu/~jwade/tutorial/cadence_mixed-signal/ams_tutorial.html | here ]] | ||
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