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* [[http://www.smta.org/files/acronym_glossary.pdf|Glossary of Acronyms Relevant to Electronics Manufacturing]] | * [[http://www.smta.org/files/acronym_glossary.pdf|Glossary of Acronyms Relevant to Electronics Manufacturing]] | ||
* [[http://www.acronym-guide.com/technology-acronyms.php|Technology, Electronics & Video Game Acronyms]] | * [[http://www.acronym-guide.com/technology-acronyms.php|Technology, Electronics & Video Game Acronyms]] | ||
- | * ... | + | * [[http://www.vlsiencyclopedia.com/p/vlsi-glossary.html|VLSI Glossary (VLSI-encyclopedia)]] |
===== A ===== | ===== A ===== | ||
Linea 85: | Linea 85: | ||
**ASIC** - Application Specific Integrated Circuit | **ASIC** - Application Specific Integrated Circuit | ||
+ | |||
+ | **ASK** - Amplitude-shift keying | ||
**<nowiki>ASP</nowiki>** - Analog Signal Processing | **<nowiki>ASP</nowiki>** - Analog Signal Processing | ||
Linea 99: | Linea 101: | ||
===== B ===== | ===== B ===== | ||
+ | |||
**BEOL** - Back-End Of Line | **BEOL** - Back-End Of Line | ||
Linea 109: | Linea 112: | ||
**BIT** - Built-In Test | **BIT** - Built-In Test | ||
+ | |||
+ | **bit** - binary digit | ||
+ | |||
+ | **BJT** - Bipolar Junction Transistor | ||
**BL** - Base-Line | **BL** - Base-Line | ||
Linea 114: | Linea 121: | ||
**BLH** - Base-Line Holder | **BLH** - Base-Line Holder | ||
- | **BJT** - Bipolar Junction Transistor | + | **BNF** - Backus-Naur Form |
+ | |||
+ | **BOM** - Bill Of Material | ||
**bpi** - bits per inch (HD drive) | **bpi** - bits per inch (HD drive) | ||
**Bpi** - byte per inch (HD drive) | **Bpi** - byte per inch (HD drive) | ||
+ | |||
+ | **BW** - Band-Width | ||
**BX** - Bunch Crossing | **BX** - Bunch Crossing | ||
- | **BW** - Band-Width | + | **byte** - 8 bits (1B = 8b) |
===== C ===== | ===== C ===== | ||
Linea 169: | Linea 180: | ||
**CPC** - Charge-Pump Circuit | **CPC** - Charge-Pump Circuit | ||
+ | |||
+ | **crumb** - 2 bits | ||
**CSV** - (//file ext.//) Comma-Separated Values | **CSV** - (//file ext.//) Comma-Separated Values | ||
**CT** - Continuous Time | **CT** - Continuous Time | ||
+ | |||
+ | **CTS** - Clock Tree Synthesis | ||
**<nowiki>CVS</nowiki>** - Concurrent Versioning System | **<nowiki>CVS</nowiki>** - Concurrent Versioning System | ||
Linea 196: | Linea 211: | ||
**dc** - (//Spectre//) DC analysis | **dc** - (//Spectre//) DC analysis | ||
- | **dcmatch** (//Spectre//) ???? analysis | + | **dcmatch** - (//Spectre//) ???? analysis |
+ | |||
+ | **deckle** - 10 bits | ||
+ | |||
+ | **DEF** - (//Cadence//) Design-Exchange Format | ||
+ | |||
+ | **DDS** - Direct Digital Synthesis | ||
**D-FF** - Delay Flip-Flop (D-type Flip-Flop) | **D-FF** - Delay Flip-Flop (D-type Flip-Flop) | ||
Linea 209: | Linea 230: | ||
**Diva** - //Cadence//'s layout verification tool | **Diva** - //Cadence//'s layout verification tool | ||
+ | |||
+ | **DLL** - Delay-Locked Loop | ||
**DNL** - Differential Non-Linearity | **DNL** - Differential Non-Linearity | ||
Linea 225: | Linea 248: | ||
**DT** - Discrete Time | **DT** - Discrete Time | ||
+ | |||
+ | **DTL** - Diode-Transistor Logic | ||
**DUT** - Device Under Test | **DUT** - Device Under Test | ||
+ | |||
+ | **dynner** - 32 bits | ||
+ | |||
+ | **DUV** - Device Under Verification | ||
+ | |||
===== E ===== | ===== E ===== | ||
**EAROM** - Eletrically Alterable Read Only Memory | **EAROM** - Eletrically Alterable Read Only Memory | ||
+ | |||
+ | **ECL** - Emitter-coupled logic | ||
**EDA** - Electronic Design Automation | **EDA** - Electronic Design Automation | ||
Linea 285: | Linea 317: | ||
**FIR** - (//digital filters//) Finite Impulse Response | **FIR** - (//digital filters//) Finite Impulse Response | ||
+ | |||
+ | **FM** - Frequency Modulation | ||
**FOM** - Figure Of Merit | **FOM** - Figure Of Merit | ||
Linea 295: | Linea 329: | ||
**FS** - (//corner//) Fast NMOS, Slow PMOS | **FS** - (//corner//) Fast NMOS, Slow PMOS | ||
+ | |||
+ | **FSK** - Frequency-shift keying | ||
**FSM** - Finite-State-Machine | **FSM** - Finite-State-Machine | ||
Linea 366: | Linea 402: | ||
**IP address** - Internet Protocol address | **IP address** - Internet Protocol address | ||
+ | |||
+ | **ISI** - Inter-symbol interference | ||
**<nowiki>ISP</nowiki>** - In-System Programming | **<nowiki>ISP</nowiki>** - In-System Programming | ||
Linea 394: | Linea 432: | ||
**LED** - Light-Emitting Diode | **LED** - Light-Emitting Diode | ||
+ | |||
+ | **LEF** - (//Cadence//) Library Exchange Format | ||
**LET** - Linear Energy Transfer (//dE/dx// ) | **LET** - Linear Energy Transfer (//dE/dx// ) | ||
Linea 458: | Linea 498: | ||
===== N ===== | ===== N ===== | ||
+ | |||
+ | **N/A** - Not applicable (or not available) | ||
**nch** - NMOS transistor | **nch** - NMOS transistor | ||
Linea 464: | Linea 506: | ||
**nfet** - NMOS transistor | **nfet** - NMOS transistor | ||
+ | |||
+ | **nibble** - (also //nybble//) 4 bits | ||
+ | |||
+ | **nickle** - 5 bits | ||
**NIM** - Nuclear and Instrument Methods | **NIM** - Nuclear and Instrument Methods | ||
Linea 472: | Linea 518: | ||
**NTF** - Noise Transfer Function | **NTF** - Noise Transfer Function | ||
+ | |||
+ | |||
===== O ===== | ===== O ===== | ||
Linea 504: | Linea 552: | ||
**PDK** - [[ http://en.wikipedia.org/wiki/Process_design_kit | Process Design Kit ]] | **PDK** - [[ http://en.wikipedia.org/wiki/Process_design_kit | Process Design Kit ]] | ||
+ | |||
+ | **PD** - Phase Detector | ||
**PDP** - Power-Delay Product | **PDP** - Power-Delay Product | ||
Linea 602: | Linea 652: | ||
**RTL** - Register Transfer Level | **RTL** - Register Transfer Level | ||
+ | |||
+ | **RTL** - Resistor-transistor logic | ||
**RVE** - (//Calibre//) Results Viewing Environment | **RVE** - (//Calibre//) Results Viewing Environment | ||
Linea 608: | Linea 660: | ||
**SADD** - Start Address | **SADD** - Start Address | ||
+ | |||
+ | **SAW** - Surface acoustic wave | ||
**SDD** - Silicon Drift Detector | **SDD** - Silicon Drift Detector | ||
Linea 702: | Linea 756: | ||
**TT** - (//corner//) Typical NMOS, Typical PMOS | **TT** - (//corner//) Typical NMOS, Typical PMOS | ||
+ | |||
+ | **TTL** - Transistor-transistor logic | ||
**TVF** - (//Calibre//) TCL Verification Format | **TVF** - (//Calibre//) TCL Verification Format | ||
**tw** - triple-well transistor | **tw** - triple-well transistor | ||
+ | |||
+ | **tydbit** - (also //tayste//) 2 bits | ||
===== U ===== | ===== U ===== |