Differenze
Queste sono le differenze tra la revisione selezionata e la versione attuale della pagina.
Entrambe le parti precedenti la revisione Revisione precedente Prossima revisione | Revisione precedente Prossima revisione Entrambe le parti successive la revisione | ||
vlsi:theses:archive:master [16/04/2018 14:35] pacher [A.A. 2016/2017] |
vlsi:theses:archive:master [24/08/2018 21:09] pacher [A.A. 2016/2017] |
||
---|---|---|---|
Linea 7: | Linea 7: | ||
+ | |||
+ | |||
+ | |||
+ | ====== A.A. 2017/2018 ====== | ||
Linea 13: | Linea 17: | ||
//**Lorenzo Piccolo**// \\ | //**Lorenzo Piccolo**// \\ | ||
//Analog Front-end Design in Deep Sub-micron CMOS Technology for Timing application in Pixel Detectors// | //Analog Front-end Design in Deep Sub-micron CMOS Technology for Timing application in Pixel Detectors// | ||
- | **{{:vlsi:theses:archive:master:lorenzo_piccolo_master_thesis.pdf|PDF}}**\\ | + | **{{:vlsi:theses:archive:master:lorenzo_piccolo_master_thesis.pdf|[PDF]}}**\\ |
+ | Final defense presentation: **{{:vlsi:theses:archive:master:lorenzo_piccolo_defense.pdf|[PDF]}}**\\ | ||
Supervisor: __A. Rivetti__ | Supervisor: __A. Rivetti__ | ||
+ | //**Raffaele Aron Giampaolo**//. \\ | ||
+ | //Cryogenic CMOS Front-End for Dark Matter Detection Research and Development// \\ | ||
+ | Final defence presentation: **{{:vlsi:theses:archive:master:defense:aron_giampaolo_defense.pdf|[PDF]}}**\\ | ||
+ | Supervisor: __A. Rivetti__ | ||
//**Andrea Di Salvo**// \\ | //**Andrea Di Salvo**// \\ | ||
//Modelling, implementation and self-calibration methods for a 12-bit SAR ADC// | //Modelling, implementation and self-calibration methods for a 12-bit SAR ADC// | ||
- | **{{:vlsi:theses:archive:master:andrea_disalvo_master_thesis.pdf|PDF}}**\\ | + | **{{:vlsi:theses:archive:master:andrea_disalvo_master_thesis.pdf|[PDF]}}**\\ |
+ | Final defence presentation: **FIXME** \\ | ||
Supervisor: __A. Rivetti__ | Supervisor: __A. Rivetti__ | ||
- | |||
====== A.A. 2015/2016 ====== | ====== A.A. 2015/2016 ====== | ||
+ | //**Cecilia Giovinazzo**// \\ | ||
+ | //Study of an FPGA interface for a serial communication link at high speed// | ||
+ | {{ :vlsi:theses:archive:master:cecilia_giovinazzo_master_thesis.pdf|PDF}} \\ | ||
+ | Final defense presentation: **FIXME** \\ | ||
+ | Supervisors: __M. Greco__, P. De Remigis \\ | ||
====== A.A. 2014/2015 ====== | ====== A.A. 2014/2015 ====== | ||
Linea 35: | Linea 49: | ||
Supervisors: __A. Solano__, N. Cartiglia | Supervisors: __A. Solano__, N. Cartiglia | ||
- | |||
- | |||
- | {{ :vlsi:theses:archive:master:luca_pacher_master_thesis.pdf}} | ||
====== A.A. 2012/2013 ====== | ====== A.A. 2012/2013 ====== |