Differenze
Queste sono le differenze tra la revisione selezionata e la versione attuale della pagina.
Entrambe le parti precedenti la revisione Revisione precedente Prossima revisione | Revisione precedente | ||
vlsi:resources:verilog [19/04/2014 15:39] pacher |
vlsi:resources:verilog [19/05/2014 14:47] (versione attuale) pacher |
||
---|---|---|---|
Linea 4: | Linea 4: | ||
[ __[[vlsi:home|Home]]__ ] | [ __[[vlsi:home|Home]]__ ] | ||
[ __[[vlsi:workbook|Design WorkBook]]__ ] | [ __[[vlsi:workbook|Design WorkBook]]__ ] | ||
+ | [ __[[vlsi:resources:books|Books]]__ ] | ||
+ | References to documentation, books, online courses, training solutions etc.. | ||
+ | |||
+ | |||
+ | |||
+ | ====== Literature ====== | ||
+ | |||
+ | IEEE standards: | ||
+ | |||
+ | * IEEE std. 1364-1995, //IEEE Standard Verilog Hardware Description Language// | ||
+ | * IEEE std. 1364-2001, //IEEE Standard Verilog Language Reference Manual// | ||
+ | * IEEE std. 1076-2002, //IEEE Standard Verilog Language Reference Manual// | ||
+ | |||
+ | |||
+ | \\ | ||
+ | Books: | ||
+ | |||
+ | * D.E. Thomas and P. Moorby 1991, //The Verilog Hardware Description Language// | ||
+ | * S. Palnitkar 1996, //Verilog HDL: A Guide to Digital Design and Synthesis// | ||
+ | * S. Brown and Z. Vranesic 2002, //Fundamentals of Digital Logic with Verilog Design// | ||
+ | * Z. Navabi 2006, //Verilog Digital System Design// | ||
+ | * ... | ||
+ | * ... | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | ====== Self training and courses (free!) ====== | ||
+ | |||
+ | [[http://www.verilog.com/]] \\ | ||
+ | [[http://vol.verilog.com/]] \\ | ||
+ | [[http://www.asic-world.com/verilog/index.html]] \\ | ||
+ | [[http://sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_top.html]] | ||
+ | |||
+ | |||
+ | |||
+ | \\ | ||
+ | YouTube lectures (playlists): | ||
+ | |||
+ | [[http://www.youtube.com/playlist?list=PLScWdLzHpkAfbPhzz1NKHDv2clv1SgsMo]] (by EDA Playground) \\ | ||
+ | [[http://www.youtube.com/watch?v=PybxgAroozA]] (1/20, by Kirk Weedman) | ||
+ | |||
+ | |||
+ | \\ | ||
+ | Xilinx training: | ||
+ | |||
+ | [[http://www.xilinx.com/training/]] \\ | ||
+ | [[http://www.xilinx.com/training/languages/basic-hdl-coding-techniques-video.htm]] | ||
+ | |||
+ | \\ | ||
+ | Altera training: | ||
+ | |||
+ | |||
+ | ====== Other online training solutions (priced) ====== | ||
+ | |||
+ | [[http://www.computerbasededucation.com/verilog101.htm]] | ||
+ | |||
+ | |||
+ | |||
+ | |||
+ | |||
+ | ====== Coding resources ====== | ||
+ | |||
+ | [[http://www.testbench.in/]] | ||
+ | |||
+ | |||
+ | |||
+ | ======= Lecture notes ====== | ||
====== ====== | ====== ====== | ||
Linea 12: | Linea 80: | ||
---- | ---- | ||
- | Last update: [[pacher@NOSPAMto.infn.it|Luca Pacher] - Apr 19, 2014 | + | Last update: [[pacher@NOSPAMto.infn.it|Luca Pacher]] - Apr 19, 2014 |
~~NOTOC~~ | ~~NOTOC~~ |