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--- vlsi:resources:systemverilog [02/07/2015 22:49]
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+++ vlsi:resources:systemverilog [14/07/2015 10:25] (versione attuale)
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 [ __[[vlsi:workbook|Design WorkBook]]__ ]
 [ __[[vlsi:resources:books|Books]]__ ]
+//IEEE std 1800-2012//  \\
+[[http://www.eda.org/sv/SystemVerilog_3.1a.pdf|SystemVerilog 3.1a Language Reference Manual]]
+//OVM/UVM User's Guide//
+\\
+====== Syntax highlighting for the Gedit text editor ======
+**1.** make a copy of the Verilog language style
+''/usr/share/gtksourceview-2.0/language-specs/verilog.lang''
+**2.** modify the language id as
+<code>
+<language id="systemverilog" _name="SystemVerilog" version="2.0" _section="Sources">
+</code>
+and
+<code>
+   <context id="systemverilog">      <!-- modified from verilog to systemverilog -->
+      <include>
+        <context ref="line-comment"/>
+        <context ref="block-comment"/>
+        <context ref="close-comment-outside-comment"/>
+        <context ref="compiler-directive"/>
+        <context ref="keywords"/>
+        <context ref="gates"/>
+        <context ref="types"/>
+        <context ref="binary-number"/>
+        <context ref="octal-number"/>
+        <context ref="decimal-number"/>
+        <context ref="hexadecimal-number"/>
+      </include>
+    </context>
+</code>
+**3.** change the default file extension
+<code>
+<property name="globs">*.sv</property>
+</code>
+**4.** add new SystemVerilog reserved words by following the <nowiki>XML</nowiki> syntax
+<code>
+<keyword>word</keyword>
+</code>