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vlsi:resources:lectures:berkeley:ee141 [28/07/2014 04:30]
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vlsi:resources:lectures:berkeley:ee141 [03/02/2015 16:35] (versione attuale)
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    * [[http://​m.youtube.com/​watch?​v=CblvA1I8P9Q|Lecture 19 - Ratioed logic (contd.), differential cascode voltage switch logic, pass-transistor logic, transmission gate]]    * [[http://​m.youtube.com/​watch?​v=CblvA1I8P9Q|Lecture 19 - Ratioed logic (contd.), differential cascode voltage switch logic, pass-transistor logic, transmission gate]]
    * [[http://​m.youtube.com/​watch?​v=9pix5ClcB3Y|Lecture 20 - Transmission gate (contd.), multiplexer,​ dynamic logic]]    * [[http://​m.youtube.com/​watch?​v=9pix5ClcB3Y|Lecture 20 - Transmission gate (contd.), multiplexer,​ dynamic logic]]
-   * [[http://​m.youtube.com/​watch?​v=AU2nwriT23I|Lecture 21 - CMOS full adder design techniques]]+   * [[http://​m.youtube.com/​watch?​v=AU2nwriT23I|Lecture 21 - Full adder design techniques ​(static, dynamic)]] 
 +   * [[http://​m.youtube.com/​watch?​v=4H5H9i3kylc|Lecture 22 - Full adder design (contd.), multipliers]] 
 +   * [[http://​m.youtube.com/​watch?​v=BT9i98jquxk|Lecture 23 - Domino logic]] 
 +   * [[http://​m.youtube.com/​watch?​v=IhqE7SSsSSE|Lecture 24 - Domino logic (contd.), introduction to sequential circuits, latches and FlipFlops, setup/hold time]] 
 +   * [[http://​m.youtube.com/​watch?​v=FMNP85VrwDU|Lecture 25 - Layout parasitics, C2MOS latches and FlipFlops, three-state latches and FlipFlops, timing and clock modelling for synchronous design]] 
 +   * [[http://​m.youtube.com/​watch?​v=_HQasaV-Tp4|Lecture 26 - Timimg and clock modelling for synchronous design (contd.), clock distribution]] 
 +   * [[http://​m.youtube.com/​watch?​v=QEsarUd6P5o|Lecture 27 - Clock distribution (contd.), chip packaging, ESD protection, I/O PADs, IR drops, electromigration,​ power distribution,​ ROM cells]] 
 + 
  
  
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-Last update: ​+Last update: ​[[pacher@to.infn.it|Luca Pacher]] - Jul 28, 2014
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