Differenze
Queste sono le differenze tra la revisione selezionata e la versione attuale della pagina.
Entrambe le parti precedenti la revisione Revisione precedente Prossima revisione | Revisione precedente | ||
vlsi:resources:books [13/12/2015 17:23] panati |
vlsi:resources:books [04/01/2016 12:09] (versione attuale) pacher |
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* [[vlsi:resources:books#digital_electronics_and_logic_design|Digital electronics and logic design]] | * [[vlsi:resources:books#digital_electronics_and_logic_design|Digital electronics and logic design]] | ||
* [[vlsi:resources:books#verilog_and_vhdl_programming|Verilog and VHDL programming]] | * [[vlsi:resources:books#verilog_and_vhdl_programming|Verilog and VHDL programming]] | ||
- | * [[vlsi:resources:books#digital_ic_design|Digital IC design]] | + | * [[vlsi:resources:books#digital_synthesis|Digital synthesis]] |
+ | * [[vlsi:resources:books#digital_cmos_ic_design|Digital CMOS IC design]] | ||
* [[vlsi:resources:books#vlsi_design_and_layout|VLSI design and layout]] | * [[vlsi:resources:books#vlsi_design_and_layout|VLSI design and layout]] | ||
* [[vlsi:resources:books#fpga_programming|FPGA programming]] | * [[vlsi:resources:books#fpga_programming|FPGA programming]] | ||
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* J. Bergeron, //Writing Testbenches: Functional Verification of HDL Models// [x] | * J. Bergeron, //Writing Testbenches: Functional Verification of HDL Models// [x] | ||
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+ | ====== Digital synthesis ====== | ||
+ | |||
+ | * S. Gangadaran and S. Churiwala, //Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)// [x] | ||
======= Digital CMOS IC design ======= | ======= Digital CMOS IC design ======= |