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| Entrambe le parti precedenti la revisione Revisione precedente Prossima revisione | Revisione precedente | ||
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vlsi:resources:books [04/11/2015 17:13] panati |
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| * [[vlsi:resources:books#digital_electronics_and_logic_design|Digital electronics and logic design]] | * [[vlsi:resources:books#digital_electronics_and_logic_design|Digital electronics and logic design]] | ||
| * [[vlsi:resources:books#verilog_and_vhdl_programming|Verilog and VHDL programming]] | * [[vlsi:resources:books#verilog_and_vhdl_programming|Verilog and VHDL programming]] | ||
| - | * [[vlsi:resources:books#digital_ic_design|Digital IC design]] | + | * [[vlsi:resources:books#digital_synthesis|Digital synthesis]] |
| + | * [[vlsi:resources:books#digital_cmos_ic_design|Digital CMOS IC design]] | ||
| * [[vlsi:resources:books#vlsi_design_and_layout|VLSI design and layout]] | * [[vlsi:resources:books#vlsi_design_and_layout|VLSI design and layout]] | ||
| * [[vlsi:resources:books#fpga_programming|FPGA programming]] | * [[vlsi:resources:books#fpga_programming|FPGA programming]] | ||
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| * R.K. Brayton et al., //Logic Minimization Algorithms for VLSI Synthesis// [x] | * R.K. Brayton et al., //Logic Minimization Algorithms for VLSI Synthesis// [x] | ||
| * P.K. Lala, //Principles of Modern Digital Design// | * P.K. Lala, //Principles of Modern Digital Design// | ||
| + | * R.F. Tinder, //Asynchronous Sequential Machine Design and Analysis: A Comprehensive Development of the Design and Analysis of Clock-Independent State Machines and Systems// | ||
| + | * J. Bainbridge, //Asynchronous System-on-Chip Interconnect// | ||
| + | * H. Bhatnagar, //Advanced ASIC Chip Synthesis Using Synopsys Tools// | ||
| + | * H. Bhathagar, //Advanced ASIC Chip Synthesis Using Synopsys, Design Compiler and PrimeTime// | ||
| ====== Verilog and VHDL programming ====== | ====== Verilog and VHDL programming ====== | ||
| Linea 227: | Linea 231: | ||
| * J. Bergeron, //Writing Testbenches: Functional Verification of HDL Models// [x] | * J. Bergeron, //Writing Testbenches: Functional Verification of HDL Models// [x] | ||
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| + | |||
| + | ====== Digital synthesis ====== | ||
| + | |||
| + | * S. Gangadaran and S. Churiwala, //Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)// [x] | ||
| ======= Digital CMOS IC design ======= | ======= Digital CMOS IC design ======= | ||